OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [run/] [run_all] - Rev 43

Go to most recent revision | Compare with Previous | Blame | View Log

#!/bin/csh -f

#format
# run_modesim <Option1> <Option2> 
#    Example ./run_modelsim core SDR_16BIT
#
# Option-1: 
#        core - Run the SDRAM core level test case
#        top  - Run the SDRAM Top level test case 
# Option-2: 
#        SDR-16BIT  - Run 16 Bit SDRAM Test case
#        SDR-32BIT  - Run 32 Bit SDRAM Test case
#        SDR-8BIT   - Run 8  Bit SDRAM Test case
#
#
echo "######### SDRAM CORE STAND ALONG TEST CASE ########"
echo "#############################"
echo " INITIATING SDR 16 BIT Tests"
echo ##############################
./run_modelsim core SDR_16BIT | tee ../log/core_sdr16_sim.log

echo "#############################"
echo " INITIATING SDR 32 BIT Tests"
echo ##############################
./run_modelsim core SDR_32BIT | tee ../log/core_sdr32_sim.log

echo "#############################"
echo " INITIATING SDR 8 BIT Tests"
echo ##############################
./run_modelsim core SDR_8BIT | tee ../log/core_sdr8_sim.log


echo "######### SDRAM TOP TEST CASE ########"

echo "#############################"
echo " INITIATING SDR 16 BIT Tests"
echo ##############################
./run_modelsim top SDR_16BIT | tee ../log/top_sdr16_sim.log

echo "#############################"
echo " INITIATING SDR 32 BIT Tests"
echo ##############################
./run_modelsim top SDR_32BIT | tee ../log/top_sdr32_sim.log

echo "#############################"
echo " INITIATING SDR 8 BIT Tests"
echo ##############################
./run_modelsim top SDR_8BIT | tee ../log/top_sdr8_sim.log

./regression_analysis

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.