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https://opencores.org/ocsvn/sdram_controller/sdram_controller/trunk
Subversion Repositories sdram_controller
[/] [sdram_controller/] [trunk/] [boards/] [Microblaze1600E/] [Microblaze1600E.xise] - Rev 24
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="11.2" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="../../ddr.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../ddr_parameters.vh" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../scratch.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../scratch_isim_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="PostMapSimulation"/>
<association xil_pn:name="PostRouteSimulation"/>
<association xil_pn:name="PostTranslateSimulation"/>
</file>
<file xil_pn:name="../../sdram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../sdram_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../sdram_reader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../sdram_support.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../sdram_writer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="Microblaze1600E.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation"/>
</file>
</files>
<properties>
<property xil_pn:name="Constraints Entry" xil_pn:value="Constraints Editor"/>
<property xil_pn:name="Device" xil_pn:value="xc3s1600e"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3E"/>
<property xil_pn:name="Fitter Report Format" xil_pn:value="HTML"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|scratch|impl"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/scratch"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="Microblaze1600E"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e"/>
<property xil_pn:name="Package" xil_pn:value="fg320"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL"/>
<property xil_pn:name="Project Description" xil_pn:value="Project to build a working minimal test application using the DDR controller on the Xilinx Microblaze Starter Kit FPGA developmnet board which includes a Spartan-3E 1600E device. "/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store non-default values only"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="Architecture|scratch|impl"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="Architecture|scratch_isim_tb|behavior"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="uut"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL"/>
</properties>
<bindings/>
<libraries/>
<partitions/>
</project>