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[/] [sgmii/] [trunk/] [build/] [OpenCore_MAC/] [TECH/] [altera/] [CLK_SWITCH.v.bak] - Rev 26
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//////////////////////////////////////////////////////////////////////
//// ////
//// CLK_SWITCH.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao (gaojon@yahoo.com) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2006/06/22 09:01:41 Administrator
// no message
//
// Revision 1.2 2005/12/16 06:44:20 Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
// no message
//
//////////////////////////////////////////////////////////////////////
// This file can only used for simulation .
// You need to replace it with your own element according to technology
//////////////////////////////////////////////////////////////////////
module CLK_SWITCH_ALT (
input IN_0,
input IN_1,
input SW ,
output OUT
);
clk_mux altclkmux(
.clkselect(SW),
.inclk0x(IN_0),
.inclk1x(IN_1),
.outclk(OUT));
endmodule
module CLK_SWITCH (
input IN_0,
input IN_1,
input SW ,
output OUT
);
assign OUT = (SW==1'b0)?IN_0:IN_1;
endmodule
module CLK_SWITCH_ALT2 (
input IN_0,
input IN_1,
input SW ,
output OUT
);
wire clki;
assign clki = (SW==1'b0)?IN_0:IN_1;
clk_buf altclkbuf(
.inclk0x(clki),
.outclk(OUT));
endmodule