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</style></HEAD><BODY align="left" style='background-color: #ffffff;'><DIV align="left"><TABLE width="95%" border=0 cellpadding=2><TR><TD><TABLE cellpadding=2 border=0 ><TR><WIZARD></WIZARD><TD><H1>Generation Report - 8B10B Encoder-Decoder MegaCore Function v12.0</H1></TD></TR></TABLE></TD></TR><TR><TD><TABLE cellpadding=2 border=1 width="60%"><TR><TD><B>Entity Name</B></TD><TD>mAlt8b10benc_enc8b10b</TD></TR><TR><TD><B>Variation Name</B></TD><TD>mAlt8b10benc</TD></TR><TR><TD><B>Variation HDL</B></TD><TD>Verilog HDL</TD></TR><TR><TD><B>Output Directory</B></TD><TD>D:\JEFF\OpenCores\SGMII\trunk\src\mAltGX</TD></TR></TABLE></TD></TR><TR><TD><h2>File Summary</h2>The MegaWizard interface is creating the following files in the output directory:</TD></TR><TR><TD><TABLE cellspacing=2 cellpadding=2 border=1 width="100%"><TR align="left"><TH align="left" align="top" width="25%"><B>File</B></TH><TH align="left"><B>Description</B></TH></TR><TR><TD>mAlt8b10benc_tb.v</TD><TD>A verilog module with the top-level demo testbench for the core.</TD></TR><TR><TD>mAlt8b10benc_run_modelsim.tcl</TD><TD>A Tcl script to automate the process of running the provided demo testbench with the IP functional simulation model.</TD></TR><TR><TD>mAlt8b10benc_constraints.tcl</TD><TD>Tool command language (Tcl) script used to set constraints.</TD></TR><TR><TD>mAlt8b10benc_enc8b10b.ocp</TD><TD>An OpenCore Plus file, needed for time limited or tethered hardware evaluation.</TD></TR><TR><TD>mAlt8b10benc_enc8b10b.v</TD><TD>Verilog HDL RTL for MegaCore variation</TD></TR><TR><TD>mAlt8b10benc.v</TD><TD>A MegaCore<small><sup>®</sup></small> function variation file, which defines a Verilog HDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software.</TD></TR><TR><TD>mAlt8b10benc.bsf</TD><TD>Quartus<small><sup>®</sup></small> II symbol file for the MegaCore function variation. You can use this file in the Quartus II block diagram editor.</TD></TR><TR><TD>mAlt8b10benc.vo</TD><TD>Verilog HDL IP functional simulation model</TD></TR><TR><TD>mAlt8b10benc.qip</TD><TD>Contains Quartus II project information for your MegaCore function variation.</TD></TR><TR><TD>mAlt8b10benc.html</TD><TD>The MegaCore function report file.</TD></TR></TABLE></TD></TR><TR><TD><h2>MegaCore Function Variation File Ports</h2><TABLE border=1 cellpadding=2 cellspacing=0 width="75%"><TR align="left"><TH align="left"><B>Name</B></TH><TH align="left"><B>Direction</B></TH><TH align="left"><B>Width</B></TH></TR><TR><TD>clk</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>reset_n</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>idle_ins</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>kin</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ena</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>datain</TD><TD>INPUT</TD><TD>8</TD></TR><TR><TD>kerr</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>dataout</TD><TD>OUTPUT</TD><TD>10</TD></TR><TR><TD>valid</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>rdin</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>rdforce</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>rdout</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>rdcascade</TD><TD>OUTPUT</TD><TD>1</TD></TR></TABLE></TD></TR></TD></TR></TABLE></DIV></BODY></HTML> Go to most recent revision | Compare with Previous | Blame | View Log