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// megafunction wizard: %ALTGX% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: alt_c3gxb // ============================================================ // File Name: mAltGX.v // Megafunction Name(s): // alt_c3gxb // // Simulation Library Files(s): // altera_mf;cycloneiv_hssi // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // // 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition // ************************************************************ //Copyright (C) 1991-2011 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Altera Program License //Subscription Agreement, Altera MegaCore Function License //Agreement, or other applicable license agreement, including, //without limitation, that your use is for the sole purpose of //programming logic devices manufactured by Altera and sold by //Altera or its authorized distributors. Please refer to the //applicable agreement for further details. //alt_c3gxb CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone IV GX" effective_data_rate="1250.0 Mbps" equalization_setting=5 equalizer_dcgain_setting=0 gxb_powerdown_width=1 loopback_mode="none" number_of_channels=1 number_of_quads=1 operation_mode="duplex" pll_bandwidth_type="auto" pll_control_width=1 pll_divide_by="1" pll_inclk_period=8000 pll_multiply_by="5" pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=0 protocol="gige" receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=0 reconfig_pll_control_width=1 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="false" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_channel_width=8 rx_common_mode="0.82v" rx_datapath_protocol="basic" rx_deskew_pattern="0" rx_digitalreset_port_width=1 rx_dwidth_factor=1 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_second_order_loop="false" rx_enable_self_test_mode="false" rx_force_signal_detect="true" rx_loop_1_digital_filter=8 rx_ppmselect=8 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="10100010010101111100" rx_rate_match_pattern2="10101011011010000011" rx_rate_match_pattern_size=20 rx_run_length=40 rx_run_length_enable="true" rx_signal_detect_loss_threshold=1 rx_signal_detect_threshold=8 rx_signal_detect_valid_threshold=14 rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="false" rx_use_external_termination="false" rx_word_aligner_num_byte=1 starting_channel_number=0 top_module_name="mAltGX" transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_bitslip_enable="false" tx_channel_width=8 tx_clkout_width=1 tx_common_mode="0.65v" tx_digitalreset_port_width=1 tx_dwidth_factor=1 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_slew_rate="medium" tx_transmit_protocol="basic" tx_use_coreclk="false" tx_use_double_data_mode="false" tx_use_external_termination="false" use_calibration_block="true" vod_ctrl_setting=4 cal_blk_clk gxb_powerdown pll_inclk pll_locked reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_disperr rx_errdetect rx_patterndetect rx_rlv rx_syncstatus tx_clkout tx_ctrlenable tx_datain tx_dataout tx_digitalreset intended_device_family="Cyclone IV GX" //VERSION_BEGIN 11.1SP2 cbx_alt_c3gxb 2012:01:25:21:13:53:SJ cbx_altclkbuf 2012:01:25:21:13:53:SJ cbx_altiobuf_bidir 2012:01:25:21:13:53:SJ cbx_altiobuf_in 2012:01:25:21:13:53:SJ cbx_altiobuf_out 2012:01:25:21:13:53:SJ cbx_altpll 2012:01:25:21:13:53:SJ cbx_cycloneii 2012:01:25:21:13:53:SJ cbx_lpm_add_sub 2012:01:25:21:13:53:SJ cbx_lpm_compare 2012:01:25:21:13:53:SJ cbx_lpm_decode 2012:01:25:21:13:53:SJ cbx_lpm_mux 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ cbx_stingray 2012:01:25:21:13:52:SJ cbx_stratix 2012:01:25:21:13:53:SJ cbx_stratixii 2012:01:25:21:13:53:SJ cbx_stratixiii 2012:01:25:21:13:53:SJ cbx_stratixv 2012:01:25:21:13:53:SJ cbx_util_mgl 2012:01:25:21:13:53:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 //synthesis_resources = altpll 1 cycloneiv_hssi_calibration_block 1 cycloneiv_hssi_cmu 1 cycloneiv_hssi_rx_pcs 1 cycloneiv_hssi_rx_pma 1 cycloneiv_hssi_tx_pcs 1 cycloneiv_hssi_tx_pma 1 //synopsys translate_off `timescale 1 ps / 1 ps //synopsys translate_on module mAltGX_alt_c3gxb ( cal_blk_clk, gxb_powerdown, pll_inclk, pll_locked, reconfig_clk, reconfig_fromgxb, reconfig_togxb, rx_analogreset, rx_ctrldetect, rx_datain, rx_dataout, rx_digitalreset, rx_disperr, rx_errdetect, rx_patterndetect, rx_rlv, rx_syncstatus, tx_clkout, tx_ctrlenable, tx_datain, tx_dataout, tx_digitalreset) ; input cal_blk_clk; input [0:0] gxb_powerdown; input [0:0] pll_inclk; output [0:0] pll_locked; input reconfig_clk; output [4:0] reconfig_fromgxb; input [3:0] reconfig_togxb; input [0:0] rx_analogreset; output [0:0] rx_ctrldetect; input [0:0] rx_datain; output [7:0] rx_dataout; input [0:0] rx_digitalreset; output [0:0] rx_disperr; output [0:0] rx_errdetect; output [0:0] rx_patterndetect; output [0:0] rx_rlv; output [0:0] rx_syncstatus; output [0:0] tx_clkout; input [0:0] tx_ctrlenable; input [7:0] tx_datain; output [0:0] tx_dataout; input [0:0] tx_digitalreset; `ifndef ALTERA_RESERVED_QIS // synopsys translate_off `endif tri0 cal_blk_clk; tri0 [0:0] gxb_powerdown; tri0 reconfig_clk; tri0 [0:0] rx_analogreset; tri0 [0:0] rx_digitalreset; tri0 [0:0] tx_ctrlenable; tri0 [7:0] tx_datain; tri0 [0:0] tx_digitalreset; `ifndef ALTERA_RESERVED_QIS // synopsys translate_on `endif parameter starting_channel_number = 0; wire [5:0] wire_pll0_clk; wire wire_pll0_fref; wire wire_pll0_icdrclk; wire wire_pll0_locked; wire wire_cal_blk0_nonusertocmu; wire wire_cent_unit0_dpriodisableout; wire wire_cent_unit0_dprioout; wire wire_cent_unit0_quadresetout; wire [3:0] wire_cent_unit0_rxanalogresetout; wire [3:0] wire_cent_unit0_rxcrupowerdown; wire [3:0] wire_cent_unit0_rxdigitalresetout; wire [3:0] wire_cent_unit0_rxibpowerdown; wire [1599:0] wire_cent_unit0_rxpcsdprioout; wire [1199:0] wire_cent_unit0_rxpmadprioout; wire [3:0] wire_cent_unit0_txanalogresetout; wire [3:0] wire_cent_unit0_txdetectrxpowerdown; wire [3:0] wire_cent_unit0_txdigitalresetout; wire [3:0] wire_cent_unit0_txdividerpowerdown; wire [3:0] wire_cent_unit0_txobpowerdown; wire [599:0] wire_cent_unit0_txpcsdprioout; wire [1199:0] wire_cent_unit0_txpmadprioout; wire wire_receive_pcs0_cdrctrllocktorefclkout; wire [1:0] wire_receive_pcs0_ctrldetect; wire [19:0] wire_receive_pcs0_dataout; wire [1:0] wire_receive_pcs0_disperr; wire [399:0] wire_receive_pcs0_dprioout; wire [1:0] wire_receive_pcs0_errdetect; wire [1:0] wire_receive_pcs0_patterndetect; wire wire_receive_pcs0_rlv; wire [1:0] wire_receive_pcs0_syncstatus; wire [7:0] wire_receive_pma0_analogtestbus; wire wire_receive_pma0_clockout; wire wire_receive_pma0_diagnosticlpbkout; wire [299:0] wire_receive_pma0_dprioout; wire wire_receive_pma0_locktorefout; wire [9:0] wire_receive_pma0_recoverdataout; wire wire_receive_pma0_reverselpbkout; wire wire_receive_pma0_signaldetect; wire wire_transmit_pcs0_clkout; wire [9:0] wire_transmit_pcs0_dataout; wire [149:0] wire_transmit_pcs0_dprioout; wire wire_transmit_pcs0_txdetectrx; wire wire_transmit_pma0_clockout; wire wire_transmit_pma0_dataout; wire [299:0] wire_transmit_pma0_dprioout; wire wire_transmit_pma0_seriallpbkout; wire cal_blk_powerdown; wire [0:0] cent_unit_quadresetout; wire [3:0] cent_unit_rxcrupowerdn; wire [3:0] cent_unit_rxibpowerdn; wire [1599:0] cent_unit_rxpcsdprioin; wire [1599:0] cent_unit_rxpcsdprioout; wire [1199:0] cent_unit_rxpmadprioin; wire [1199:0] cent_unit_rxpmadprioout; wire [599:0] cent_unit_tx_dprioin; wire [3:0] cent_unit_txdetectrxpowerdn; wire [3:0] cent_unit_txdividerpowerdown; wire [599:0] cent_unit_txdprioout; wire [3:0] cent_unit_txobpowerdn; wire [1199:0] cent_unit_txpmadprioin; wire [1199:0] cent_unit_txpmadprioout; wire [3:0] fixedclk_to_cmu; wire [0:0] nonusertocmu_out; wire [0:0] pll_areset; wire [0:0] pll_powerdown; wire [0:0] reconfig_togxb_busy; wire [0:0] reconfig_togxb_disable; wire [0:0] reconfig_togxb_in; wire [0:0] reconfig_togxb_load; wire [3:0] rx_analogreset_in; wire [3:0] rx_analogreset_out; wire [0:0] rx_coreclk_in; wire [0:0] rx_deserclock_in; wire [3:0] rx_digitalreset_in; wire [3:0] rx_digitalreset_out; wire [0:0] rx_enapatternalign; wire [0:0] rx_locktodata; wire [0:0] rx_locktorefclk; wire [0:0] rx_locktorefclk_wire; wire [7:0] rx_out_wire; wire [1599:0] rx_pcsdprioin_wire; wire [1599:0] rx_pcsdprioout; wire [0:0] rx_phfifordenable; wire [0:0] rx_phfiforeset; wire [0:0] rx_phfifowrdisable; wire [0:0] rx_pll_pfdrefclkout_wire; wire [4:0] rx_pma_analogtestbus; wire [0:0] rx_pma_clockout; wire [9:0] rx_pma_recoverdataout_wire; wire [1199:0] rx_pmadprioin_wire; wire [1199:0] rx_pmadprioout; wire [0:0] rx_powerdown; wire [3:0] rx_powerdown_in; wire [0:0] rx_prbscidenable; wire [0:0] rx_reverselpbkout; wire [0:0] rx_rmfiforeset; wire [0:0] rx_signaldetect_wire; wire [3:0] tx_analogreset_out; wire [0:0] tx_clkout_int_wire; wire [0:0] tx_core_clkout_wire; wire [0:0] tx_coreclk_in; wire [7:0] tx_datain_wire; wire [9:0] tx_dataout_pcs_to_pma; wire [0:0] tx_diagnosticlpbkin; wire [3:0] tx_digitalreset_in; wire [3:0] tx_digitalreset_out; wire [599:0] tx_dprioin_wire; wire [0:0] tx_forcedisp_wire; wire [0:0] tx_invpolarity; wire [0:0] tx_localrefclk; wire [0:0] tx_phfiforeset; wire [0:0] tx_pma_fastrefclk0in; wire [0:0] tx_pma_refclk0in; wire [0:0] tx_pma_refclk0inpulse; wire [1199:0] tx_pmadprioin_wire; wire [1199:0] tx_pmadprioout; wire [0:0] tx_serialloopbackout; wire [599:0] tx_txdprioout; wire [0:0] txdataout; wire [0:0] txdetectrxout; wire [0:0] w_cent_unit_dpriodisableout1w; altpll pll0 ( .activeclock(), .areset((pll_areset[0] | pll_powerdown[0])), .clk(wire_pll0_clk), .clkbad(), .clkloss(), .enable0(), .enable1(), .extclk(), .fbout(), .fref(wire_pll0_fref), .icdrclk(wire_pll0_icdrclk), .inclk({{1{1'b0}}, pll_inclk[0]}), .locked(wire_pll0_locked), .phasedone(), .scandataout(), .scandone(), .sclkout0(), .sclkout1(), .vcooverrange(), .vcounderrange() `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clkena({6{1'b1}}), .clkswitch(1'b0), .configupdate(1'b0), .extclkena({4{1'b1}}), .fbin(1'b1), .pfdena(1'b1), .phasecounterselect({4{1'b1}}), .phasestep(1'b1), .phaseupdown(1'b1), .pllena(1'b1), .scanaclr(1'b0), .scanclk(1'b0), .scanclkena(1'b1), .scandata(1'b0), .scanread(1'b0), .scanwrite(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif ); defparam pll0.bandwidth_type = "AUTO", pll0.clk0_divide_by = 1, pll0.clk0_multiply_by = 5, pll0.clk1_divide_by = 5, pll0.clk1_multiply_by = 5, pll0.clk2_divide_by = 5, pll0.clk2_duty_cycle = 20, pll0.clk2_multiply_by = 5, pll0.dpa_divide_by = 1, pll0.dpa_multiply_by = 5, pll0.inclk0_input_frequency = 8000, pll0.operation_mode = "no_compensation", pll0.intended_device_family = "Cyclone IV GX", pll0.lpm_type = "altpll"; cycloneiv_hssi_calibration_block cal_blk0 ( .calibrationstatus(), .clk(cal_blk_clk), .nonusertocmu(wire_cal_blk0_nonusertocmu), .powerdn(cal_blk_powerdown) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .testctrl(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif ); cycloneiv_hssi_cmu cent_unit0 ( .adet({4{1'b0}}), .alignstatus(), .coreclkout(), .digitaltestout(), .dpclk(reconfig_clk), .dpriodisable(reconfig_togxb_disable), .dpriodisableout(wire_cent_unit0_dpriodisableout), .dprioin(reconfig_togxb_in), .dprioload(reconfig_togxb_load), .dpriooe(), .dprioout(wire_cent_unit0_dprioout), .enabledeskew(), .fiforesetrd(), .fixedclk({{3{1'b0}}, fixedclk_to_cmu[0]}), .nonuserfromcal(nonusertocmu_out[0]), .quadreset(gxb_powerdown[0]), .quadresetout(wire_cent_unit0_quadresetout), .rdalign({4{1'b0}}), .rdenablesync(1'b0), .recovclk(1'b0), .refclkout(), .rxanalogreset({rx_analogreset_in[3:0]}), .rxanalogresetout(wire_cent_unit0_rxanalogresetout), .rxcrupowerdown(wire_cent_unit0_rxcrupowerdown), .rxctrl({4{1'b0}}), .rxctrlout(), .rxdatain({32{1'b0}}), .rxdataout(), .rxdatavalid({4{1'b0}}), .rxdigitalreset({rx_digitalreset_in[3:0]}), .rxdigitalresetout(wire_cent_unit0_rxdigitalresetout), .rxibpowerdown(wire_cent_unit0_rxibpowerdown), .rxpcsdprioin({cent_unit_rxpcsdprioin[1599:0]}), .rxpcsdprioout(wire_cent_unit0_rxpcsdprioout), .rxphfifox4byteselout(), .rxphfifox4rdenableout(), .rxphfifox4wrclkout(), .rxphfifox4wrenableout(), .rxpmadprioin({cent_unit_rxpmadprioin[1199:0]}), .rxpmadprioout(wire_cent_unit0_rxpmadprioout), .rxpowerdown({rx_powerdown_in[3:0]}), .rxrunningdisp({4{1'b0}}), .syncstatus({4{1'b0}}), .testout(), .txanalogresetout(wire_cent_unit0_txanalogresetout), .txctrl({4{1'b0}}), .txctrlout(), .txdatain({32{1'b0}}), .txdataout(), .txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown), .txdigitalreset({tx_digitalreset_in[3:0]}), .txdigitalresetout(wire_cent_unit0_txdigitalresetout), .txdividerpowerdown(wire_cent_unit0_txdividerpowerdown), .txobpowerdown(wire_cent_unit0_txobpowerdown), .txpcsdprioin({cent_unit_tx_dprioin[599:0]}), .txpcsdprioout(wire_cent_unit0_txpcsdprioout), .txphfifox4byteselout(), .txphfifox4rdclkout(), .txphfifox4rdenableout(), .txphfifox4wrenableout(), .txpmadprioin({cent_unit_txpmadprioin[1199:0]}), .txpmadprioout(wire_cent_unit0_txpmadprioout) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .pmacramtest(1'b0), .refclkdig(1'b0), .rxcoreclk(1'b0), .rxphfifordenable(1'b1), .rxphfiforeset(1'b0), .rxphfifowrdisable(1'b0), .scanclk(1'b0), .scanmode(1'b0), .scanshift(1'b0), .testin({2000{1'b0}}), .txclk(1'b0), .txcoreclk(1'b0), .txphfiforddisable(1'b0), .txphfiforeset(1'b0), .txphfifowrenable(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif ); defparam cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8, cent_unit0.auto_spd_phystatus_notify_count = 0, cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1), cent_unit0.dprio_config_mode = 6'h01, cent_unit0.in_xaui_mode = "false", cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1), cent_unit0.rx0_channel_bonding = "none", cent_unit0.rx0_clk1_mux_select = "recovered clock", cent_unit0.rx0_clk2_mux_select = "local reference clock", cent_unit0.rx0_ph_fifo_reg_mode = "false", cent_unit0.rx0_rd_clk_mux_select = "core clock", cent_unit0.rx0_recovered_clk_mux_select = "recovered clock", cent_unit0.rx0_reset_clock_output_during_digital_reset = "false", cent_unit0.rx0_use_double_data_mode = "false", cent_unit0.tx0_channel_bonding = "none", cent_unit0.tx0_rd_clk_mux_select = "central", cent_unit0.tx0_reset_clock_output_during_digital_reset = "false", cent_unit0.tx0_use_double_data_mode = "false", cent_unit0.tx0_wr_clk_mux_select = "core_clk", cent_unit0.use_coreclk_out_post_divider = "false", cent_unit0.use_deskew_fifo = "false", cent_unit0.lpm_type = "cycloneiv_hssi_cmu"; cycloneiv_hssi_rx_pcs receive_pcs0 ( .a1a2size(1'b0), .a1a2sizeout(), .a1detect(), .a2detect(), .adetectdeskew(), .alignstatus(1'b0), .alignstatussync(1'b0), .alignstatussyncout(), .bistdone(), .bisterr(), .bitslipboundaryselectout(), .byteorderalignstatus(), .cdrctrlearlyeios(), .cdrctrllocktorefcl((reconfig_togxb_busy | rx_locktorefclk[0])), .cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout), .clkout(), .coreclk(rx_coreclk_in[0]), .coreclkout(), .ctrldetect(wire_receive_pcs0_ctrldetect), .datain(rx_pma_recoverdataout_wire[9:0]), .dataout(wire_receive_pcs0_dataout), .dataoutfull(), .digitalreset(rx_digitalreset_out[0]), .disperr(wire_receive_pcs0_disperr), .dpriodisable(w_cent_unit_dpriodisableout1w[0]), .dprioin(rx_pcsdprioin_wire[399:0]), .dprioout(wire_receive_pcs0_dprioout), .enabledeskew(1'b0), .enabyteord(1'b0), .enapatternalign(rx_enapatternalign[0]), .errdetect(wire_receive_pcs0_errdetect), .fifordin(1'b0), .fifordout(), .fiforesetrd(1'b0), .hipdataout(), .hipdatavalid(), .hipelecidle(), .hipphydonestatus(), .hipstatus(), .invpol(1'b0), .k1detect(), .k2detect(), .localrefclk(tx_localrefclk[0]), .masterclk(1'b0), .parallelfdbk({20{1'b0}}), .patterndetect(wire_receive_pcs0_patterndetect), .phfifooverflow(), .phfifordenable(rx_phfifordenable[0]), .phfifordenableout(), .phfiforeset(rx_phfiforeset[0]), .phfiforesetout(), .phfifounderflow(), .phfifowrdisable(rx_phfifowrdisable[0]), .phfifowrdisableout(), .pipebufferstat(), .pipedatavalid(), .pipeelecidle(), .pipephydonestatus(), .pipepowerdown({2{1'b0}}), .pipepowerstate({4{1'b0}}), .pipestatetransdoneout(), .pipestatus(), .prbscidenable(rx_prbscidenable[0]), .quadreset(cent_unit_quadresetout[0]), .rdalign(), .recoveredclk(rx_pma_clockout[0]), .revbitorderwa(1'b0), .revparallelfdbkdata(), .rlv(wire_receive_pcs0_rlv), .rmfifodatadeleted(), .rmfifodatainserted(), .rmfifoempty(), .rmfifofull(), .rmfifordena(1'b0), .rmfiforeset(rx_rmfiforeset[0]), .rmfifowrena(1'b0), .runningdisp(), .rxdetectvalid(1'b0), .rxfound({2{1'b0}}), .signaldetect(), .signaldetected(rx_signaldetect_wire[0]), .syncstatus(wire_receive_pcs0_syncstatus), .syncstatusdeskew(), .xauidelcondmetout(), .xauififoovrout(), .xauiinsertincompleteout(), .xauilatencycompout(), .xgmctrldet(), .xgmctrlin(1'b0), .xgmdatain({8{1'b0}}), .xgmdataout(), .xgmdatavalid(), .xgmrunningdisp() `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .bitslip(1'b0), .elecidleinfersel({3{1'b0}}), .grayelecidleinferselfromtx({3{1'b0}}), .hip8b10binvpolarity(1'b0), .hipelecidleinfersel({3{1'b0}}), .hippowerdown({2{1'b0}}), .phfifox4bytesel(1'b0), .phfifox4rdenable(1'b0), .phfifox4wrclk(1'b0), .phfifox4wrenable(1'b0), .pipe8b10binvpolarity(1'b0), .pipeenrevparallellpbkfromtx(1'b0), .pmatestbusin({8{1'b0}}), .powerdn({2{1'b0}}), .refclk(1'b0), .revbyteorderwa(1'b0), .wareset(1'b0), .xauidelcondmet(1'b0), .xauififoovr(1'b0), .xauiinsertincomplete(1'b0), .xauilatencycomp(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif ); defparam receive_pcs0.align_pattern = "0101111100", receive_pcs0.align_pattern_length = 10, receive_pcs0.allow_align_polarity_inversion = "false", receive_pcs0.allow_pipe_polarity_inversion = "false", receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8, receive_pcs0.auto_spd_phystatus_notify_count = 0, receive_pcs0.bit_slip_enable = "false", receive_pcs0.byte_order_mode = "none", receive_pcs0.byte_order_pad_pattern = "0", receive_pcs0.byte_order_pattern = "0", receive_pcs0.byte_order_pld_ctrl_enable = "false", receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000, receive_pcs0.cdrctrl_enable = "false", receive_pcs0.cdrctrl_mask_cycle = 800, receive_pcs0.cdrctrl_min_lock_to_ref_cycle = 63, receive_pcs0.cdrctrl_rxvalid_mask = "false", receive_pcs0.channel_bonding = "none", receive_pcs0.channel_number = ((starting_channel_number + 0) % 4), receive_pcs0.channel_width = 8, receive_pcs0.clk1_mux_select = "recovered clock", receive_pcs0.clk2_mux_select = "local reference clock", receive_pcs0.core_clock_0ppm = "false", receive_pcs0.datapath_low_latency_mode = "false", receive_pcs0.datapath_protocol = "basic", receive_pcs0.dec_8b_10b_compatibility_mode = "true", receive_pcs0.dec_8b_10b_mode = "normal", receive_pcs0.deskew_pattern = "0", receive_pcs0.disable_auto_idle_insertion = "true", receive_pcs0.disable_running_disp_in_word_align = "false", receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false", receive_pcs0.dprio_config_mode = 6'h01, receive_pcs0.elec_idle_infer_enable = "false", receive_pcs0.elec_idle_num_com_detect = 3, receive_pcs0.enable_bit_reversal = "false", receive_pcs0.enable_self_test_mode = "false", receive_pcs0.force_signal_detect_dig = "true", receive_pcs0.hip_enable = "false", receive_pcs0.infiniband_invalid_code = 0, receive_pcs0.insert_pad_on_underflow = "false", receive_pcs0.num_align_code_groups_in_ordered_set = 1, receive_pcs0.num_align_cons_good_data = 4, receive_pcs0.num_align_cons_pat = 3, receive_pcs0.num_align_loss_sync_error = 4, receive_pcs0.ph_fifo_low_latency_enable = "true", receive_pcs0.ph_fifo_reg_mode = "false", receive_pcs0.protocol_hint = "gige", receive_pcs0.rate_match_back_to_back = "true", receive_pcs0.rate_match_delete_threshold = 13, receive_pcs0.rate_match_empty_threshold = 5, receive_pcs0.rate_match_fifo_mode = "true", receive_pcs0.rate_match_full_threshold = 20, receive_pcs0.rate_match_insert_threshold = 11, receive_pcs0.rate_match_ordered_set_based = "true", receive_pcs0.rate_match_pattern1 = "10100010010101111100", receive_pcs0.rate_match_pattern2 = "10101011011010000011", receive_pcs0.rate_match_pattern_size = 20, receive_pcs0.rate_match_reset_enable = "false", receive_pcs0.rate_match_skip_set_based = "false", receive_pcs0.rate_match_start_threshold = 7, receive_pcs0.rd_clk_mux_select = "core clock", receive_pcs0.recovered_clk_mux_select = "recovered clock", receive_pcs0.run_length = 40, receive_pcs0.run_length_enable = "true", receive_pcs0.rx_detect_bypass = "false", receive_pcs0.rx_phfifo_wait_cnt = 15, receive_pcs0.rxstatus_error_report_mode = 0, receive_pcs0.self_test_mode = "incremental", receive_pcs0.use_alignment_state_machine = "true", receive_pcs0.use_deskew_fifo = "false", receive_pcs0.use_double_data_mode = "false", receive_pcs0.use_parallel_loopback = "false", receive_pcs0.lpm_type = "cycloneiv_hssi_rx_pcs"; cycloneiv_hssi_rx_pma receive_pma0 ( .analogtestbus(wire_receive_pma0_analogtestbus), .clockout(wire_receive_pma0_clockout), .crupowerdn(cent_unit_rxcrupowerdn[0]), .datain(rx_datain[0]), .datastrobeout(), .deserclock(rx_deserclock_in[0]), .diagnosticlpbkout(wire_receive_pma0_diagnosticlpbkout), .dpriodisable(w_cent_unit_dpriodisableout1w[0]), .dprioin(rx_pmadprioin_wire[299:0]), .dprioout(wire_receive_pma0_dprioout), .freqlocked(), .locktodata(((~ reconfig_togxb_busy) & rx_locktodata[0])), .locktoref(rx_locktorefclk_wire[0]), .locktorefout(wire_receive_pma0_locktorefout), .powerdn(cent_unit_rxibpowerdn[0]), .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]), .recoverdataout(wire_receive_pma0_recoverdataout), .reverselpbkout(wire_receive_pma0_reverselpbkout), .rxpmareset(rx_analogreset_out[0]), .seriallpbkin(tx_serialloopbackout[0]), .signaldetect(wire_receive_pma0_signaldetect), .testbussel(4'b0110) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .dpashift(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif ); defparam receive_pma0.allow_serial_loopback = "false", receive_pma0.channel_number = ((starting_channel_number + 0) % 4), receive_pma0.common_mode = "0.82V", receive_pma0.deserialization_factor = 10, receive_pma0.dprio_config_mode = 6'h01, receive_pma0.effective_data_rate = "1250.0 Mbps", receive_pma0.enable_local_divider = "false", receive_pma0.enable_ltd = "false", receive_pma0.enable_ltr = "false", receive_pma0.enable_second_order_loop = "false", receive_pma0.eq_dc_gain = 0, receive_pma0.eq_setting = 5, receive_pma0.force_signal_detect = "true", receive_pma0.logical_channel_address = (starting_channel_number + 0), receive_pma0.loop_1_digital_filter = 8, receive_pma0.offset_cancellation = 1, receive_pma0.ppm_gen1_2_xcnt_en = 1, receive_pma0.ppm_post_eidle = 0, receive_pma0.ppmselect = 8, receive_pma0.protocol_hint = "gige", receive_pma0.signal_detect_hysteresis = 8, receive_pma0.signal_detect_hysteresis_valid_threshold = 14, receive_pma0.signal_detect_loss_threshold = 1, receive_pma0.termination = "OCT 100 Ohms", receive_pma0.use_external_termination = "false", receive_pma0.lpm_type = "cycloneiv_hssi_rx_pma"; cycloneiv_hssi_tx_pcs transmit_pcs0 ( .clkout(wire_transmit_pcs0_clkout), .coreclk(tx_coreclk_in[0]), .coreclkout(), .ctrlenable({{1{1'b0}}, tx_ctrlenable[0]}), .datain({{12{1'b0}}, tx_datain_wire[7:0]}), .datainfull({22{1'b0}}), .dataout(wire_transmit_pcs0_dataout), .detectrxloop(1'b0), .digitalreset(tx_digitalreset_out[0]), .dpriodisable(w_cent_unit_dpriodisableout1w[0]), .dprioin(tx_dprioin_wire[149:0]), .dprioout(wire_transmit_pcs0_dprioout), .enrevparallellpbk(1'b0), .forcedisp({{1{1'b0}}, tx_forcedisp_wire[0]}), .forceelecidleout(), .grayelecidleinferselout(), .hiptxclkout(), .invpol(tx_invpolarity[0]), .localrefclk(tx_localrefclk[0]), .parallelfdbkout(), .phfifooverflow(), .phfiforddisable(1'b0), .phfiforddisableout(), .phfiforeset(tx_phfiforeset[0]), .phfiforesetout(), .phfifounderflow(), .phfifowrenable(1'b1), .phfifowrenableout(), .pipeenrevparallellpbkout(), .pipepowerdownout(), .pipepowerstateout(), .pipestatetransdone(1'b0), .powerdn({2{1'b0}}), .quadreset(cent_unit_quadresetout[0]), .rdenablesync(), .revparallelfdbk({20{1'b0}}), .txdetectrx(wire_transmit_pcs0_txdetectrx), .xgmctrlenable(), .xgmdataout() `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .bitslipboundaryselect({5{1'b0}}), .dispval({2{1'b0}}), .elecidleinfersel({3{1'b0}}), .forceelecidle(1'b0), .hipdatain({10{1'b0}}), .hipdetectrxloop(1'b0), .hipelecidleinfersel({3{1'b0}}), .hipforceelecidle(1'b0), .hippowerdn({2{1'b0}}), .phfifox4bytesel(1'b0), .phfifox4rdclk(1'b0), .phfifox4rdenable(1'b0), .phfifox4wrenable(1'b0), .pipetxswing(1'b0), .prbscidenable(1'b0), .refclk(1'b0), .xgmctrl(1'b0), .xgmdatain({8{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif ); defparam transmit_pcs0.allow_polarity_inversion = "false", transmit_pcs0.bitslip_enable = "false", transmit_pcs0.channel_bonding = "none", transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4), transmit_pcs0.channel_width = 8, transmit_pcs0.core_clock_0ppm = "false", transmit_pcs0.datapath_low_latency_mode = "false", transmit_pcs0.datapath_protocol = "basic", transmit_pcs0.disable_ph_low_latency_mode = "false", transmit_pcs0.disparity_mode = "none", transmit_pcs0.dprio_config_mode = 6'h01, transmit_pcs0.elec_idle_delay = 6, transmit_pcs0.enable_bit_reversal = "false", transmit_pcs0.enable_idle_selection = "true", transmit_pcs0.enable_reverse_parallel_loopback = "false", transmit_pcs0.enable_self_test_mode = "false", transmit_pcs0.enc_8b_10b_compatibility_mode = "true", transmit_pcs0.enc_8b_10b_mode = "normal", transmit_pcs0.hip_enable = "false", transmit_pcs0.ph_fifo_reg_mode = "false", transmit_pcs0.prbs_cid_pattern = "false", transmit_pcs0.protocol_hint = "gige", transmit_pcs0.refclk_select = "local", transmit_pcs0.self_test_mode = "incremental", transmit_pcs0.use_double_data_mode = "false", transmit_pcs0.wr_clk_mux_select = "core_clk", transmit_pcs0.lpm_type = "cycloneiv_hssi_tx_pcs"; cycloneiv_hssi_tx_pma transmit_pma0 ( .cgbpowerdn(cent_unit_txdividerpowerdown[0]), .clockout(wire_transmit_pma0_clockout), .datain({tx_dataout_pcs_to_pma[9:0]}), .dataout(wire_transmit_pma0_dataout), .detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]), .diagnosticlpbkin(tx_diagnosticlpbkin[0]), .dpriodisable(w_cent_unit_dpriodisableout1w[0]), .dprioin(tx_pmadprioin_wire[299:0]), .dprioout(wire_transmit_pma0_dprioout), .fastrefclk0in(tx_pma_fastrefclk0in[0]), .forceelecidle(1'b0), .powerdn(cent_unit_txobpowerdn[0]), .refclk0in(tx_pma_refclk0in[0]), .refclk0inpulse(tx_pma_refclk0inpulse[0]), .reverselpbkin(rx_reverselpbkout[0]), .rxdetecten(txdetectrxout[0]), .rxdetectvalidout(), .rxfoundout(), .seriallpbkout(wire_transmit_pma0_seriallpbkout), .txpmareset(tx_analogreset_out[0]) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .rxdetectclk(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif ); defparam transmit_pma0.channel_number = ((starting_channel_number + 0) % 4), transmit_pma0.common_mode = "0.65V", transmit_pma0.dprio_config_mode = 6'h01, transmit_pma0.effective_data_rate = "1250.0 Mbps", transmit_pma0.enable_diagnostic_loopback = "false", transmit_pma0.enable_reverse_serial_loopback = "false", transmit_pma0.logical_channel_address = (starting_channel_number + 0), transmit_pma0.preemp_tap_1 = 0, transmit_pma0.protocol_hint = "gige", transmit_pma0.rx_detect = 0, transmit_pma0.serialization_factor = 10, transmit_pma0.slew_rate = "medium", transmit_pma0.termination = "OCT 100 Ohms", transmit_pma0.use_external_termination = "false", transmit_pma0.use_rx_detect = "false", transmit_pma0.vod_selection = 4, transmit_pma0.lpm_type = "cycloneiv_hssi_tx_pma"; assign cal_blk_powerdown = 1'b0, cent_unit_quadresetout = {wire_cent_unit0_quadresetout}, cent_unit_rxcrupowerdn = {wire_cent_unit0_rxcrupowerdown[3:0]}, cent_unit_rxibpowerdn = {wire_cent_unit0_rxibpowerdown[3:0]}, cent_unit_rxpcsdprioin = {{1200{1'b0}}, rx_pcsdprioout[399:0]}, cent_unit_rxpcsdprioout = {wire_cent_unit0_rxpcsdprioout[1599:0]}, cent_unit_rxpmadprioin = {{900{1'b0}}, rx_pmadprioout[299:0]}, cent_unit_rxpmadprioout = {wire_cent_unit0_rxpmadprioout[1199:0]}, cent_unit_tx_dprioin = {{450{1'b0}}, tx_txdprioout[149:0]}, cent_unit_txdetectrxpowerdn = {wire_cent_unit0_txdetectrxpowerdown[3:0]}, cent_unit_txdividerpowerdown = {wire_cent_unit0_txdividerpowerdown[3:0]}, cent_unit_txdprioout = {wire_cent_unit0_txpcsdprioout[599:0]}, cent_unit_txobpowerdn = {wire_cent_unit0_txobpowerdown[3:0]}, cent_unit_txpmadprioin = {{900{1'b0}}, tx_pmadprioout[299:0]}, cent_unit_txpmadprioout = {wire_cent_unit0_txpmadprioout[1199:0]}, fixedclk_to_cmu = {4{reconfig_clk}}, nonusertocmu_out = {wire_cal_blk0_nonusertocmu}, pll_areset = 1'b0, pll_locked = {wire_pll0_locked}, pll_powerdown = 1'b0, reconfig_fromgxb = {rx_pma_analogtestbus[4:1], wire_cent_unit0_dprioout}, reconfig_togxb_busy = reconfig_togxb[3], reconfig_togxb_disable = reconfig_togxb[1], reconfig_togxb_in = reconfig_togxb[0], reconfig_togxb_load = reconfig_togxb[2], rx_analogreset_in = {{3{1'b0}}, ((~ reconfig_togxb_busy) & rx_analogreset[0])}, rx_analogreset_out = {wire_cent_unit0_rxanalogresetout[3:0]}, rx_coreclk_in = {tx_core_clkout_wire[0]}, rx_ctrldetect = {wire_receive_pcs0_ctrldetect[0]}, rx_dataout = {rx_out_wire[7:0]}, rx_deserclock_in = {wire_pll0_icdrclk}, rx_digitalreset_in = {{3{1'b0}}, rx_digitalreset[0]}, rx_digitalreset_out = {wire_cent_unit0_rxdigitalresetout[3:0]}, rx_disperr = {wire_receive_pcs0_disperr[0]}, rx_enapatternalign = 1'b0, rx_errdetect = {wire_receive_pcs0_errdetect[0]}, rx_locktodata = 1'b0, rx_locktorefclk = 1'b0, rx_locktorefclk_wire = {wire_receive_pcs0_cdrctrllocktorefclkout}, rx_out_wire = {wire_receive_pcs0_dataout[7:0]}, rx_patterndetect = {wire_receive_pcs0_patterndetect[0]}, rx_pcsdprioin_wire = {{1200{1'b0}}, cent_unit_rxpcsdprioout[399:0]}, rx_pcsdprioout = {{1200{1'b0}}, wire_receive_pcs0_dprioout}, rx_phfifordenable = 1'b1, rx_phfiforeset = 1'b0, rx_phfifowrdisable = 1'b0, rx_pll_pfdrefclkout_wire = {wire_pll0_fref}, rx_pma_analogtestbus = {{4{1'b0}}, wire_receive_pma0_analogtestbus[6]}, rx_pma_clockout = {wire_receive_pma0_clockout}, rx_pma_recoverdataout_wire = {wire_receive_pma0_recoverdataout[9:0]}, rx_pmadprioin_wire = {{900{1'b0}}, cent_unit_rxpmadprioout[299:0]}, rx_pmadprioout = {{900{1'b0}}, wire_receive_pma0_dprioout}, rx_powerdown = 1'b0, rx_powerdown_in = {{3{1'b0}}, rx_powerdown[0]}, rx_prbscidenable = 1'b0, rx_reverselpbkout = {wire_receive_pma0_reverselpbkout}, rx_rlv = {wire_receive_pcs0_rlv}, rx_rmfiforeset = 1'b0, rx_signaldetect_wire = {wire_receive_pma0_signaldetect}, rx_syncstatus = {wire_receive_pcs0_syncstatus[0]}, tx_analogreset_out = {wire_cent_unit0_txanalogresetout[3:0]}, tx_clkout = {tx_core_clkout_wire[0]}, tx_clkout_int_wire = {wire_transmit_pcs0_clkout}, tx_core_clkout_wire = {tx_clkout_int_wire[0]}, tx_coreclk_in = {tx_clkout_int_wire[0]}, tx_datain_wire = {tx_datain[7:0]}, tx_dataout = {txdataout[0]}, tx_dataout_pcs_to_pma = {wire_transmit_pcs0_dataout[9:0]}, tx_diagnosticlpbkin = {wire_receive_pma0_diagnosticlpbkout}, tx_digitalreset_in = {{3{1'b0}}, tx_digitalreset[0]}, tx_digitalreset_out = {wire_cent_unit0_txdigitalresetout[3:0]}, tx_dprioin_wire = {{450{1'b0}}, cent_unit_txdprioout[149:0]}, tx_forcedisp_wire = {1'b0}, tx_invpolarity = 1'b0, tx_localrefclk = {wire_transmit_pma0_clockout}, tx_phfiforeset = 1'b0, tx_pma_fastrefclk0in = {wire_pll0_clk[0]}, tx_pma_refclk0in = {wire_pll0_clk[1]}, tx_pma_refclk0inpulse = {wire_pll0_clk[2]}, tx_pmadprioin_wire = {{900{1'b0}}, cent_unit_txpmadprioout[299:0]}, tx_pmadprioout = {{900{1'b0}}, wire_transmit_pma0_dprioout}, tx_serialloopbackout = {wire_transmit_pma0_seriallpbkout}, tx_txdprioout = {{450{1'b0}}, wire_transmit_pcs0_dprioout}, txdataout = {wire_transmit_pma0_dataout}, txdetectrxout = {wire_transmit_pcs0_txdetectrx}, w_cent_unit_dpriodisableout1w = {wire_cent_unit0_dpriodisableout}; endmodule //mAltGX_alt_c3gxb //VALID FILE // synopsys translate_off `timescale 1 ps / 1 ps // synopsys translate_on module mAltGX ( cal_blk_clk, gxb_powerdown, pll_inclk, reconfig_clk, reconfig_togxb, rx_analogreset, rx_datain, rx_digitalreset, tx_ctrlenable, tx_datain, tx_digitalreset, pll_locked, reconfig_fromgxb, rx_ctrldetect, rx_dataout, rx_disperr, rx_errdetect, rx_patterndetect, rx_rlv, rx_syncstatus, tx_clkout, tx_dataout); input cal_blk_clk; input [0:0] gxb_powerdown; input [0:0] pll_inclk; input reconfig_clk; input [3:0] reconfig_togxb; input [0:0] rx_analogreset; input [0:0] rx_datain; input [0:0] rx_digitalreset; input [0:0] tx_ctrlenable; input [7:0] tx_datain; input [0:0] tx_digitalreset; output [0:0] pll_locked; output [4:0] reconfig_fromgxb; output [0:0] rx_ctrldetect; output [7:0] rx_dataout; output [0:0] rx_disperr; output [0:0] rx_errdetect; output [0:0] rx_patterndetect; output [0:0] rx_rlv; output [0:0] rx_syncstatus; output [0:0] tx_clkout; output [0:0] tx_dataout; parameter starting_channel_number = 0; wire [0:0] sub_wire0; wire [0:0] sub_wire1; wire [4:0] sub_wire2; wire [0:0] sub_wire3; wire [0:0] sub_wire4; wire [0:0] sub_wire5; wire [7:0] sub_wire6; wire [0:0] sub_wire7; wire [0:0] sub_wire8; wire [0:0] sub_wire9; wire [0:0] sub_wire10; wire [0:0] rx_patterndetect = sub_wire0[0:0]; wire [0:0] pll_locked = sub_wire1[0:0]; wire [4:0] reconfig_fromgxb = sub_wire2[4:0]; wire [0:0] rx_disperr = sub_wire3[0:0]; wire [0:0] rx_syncstatus = sub_wire4[0:0]; wire [0:0] rx_ctrldetect = sub_wire5[0:0]; wire [7:0] rx_dataout = sub_wire6[7:0]; wire [0:0] rx_errdetect = sub_wire7[0:0]; wire [0:0] rx_rlv = sub_wire8[0:0]; wire [0:0] tx_clkout = sub_wire9[0:0]; wire [0:0] tx_dataout = sub_wire10[0:0]; mAltGX_alt_c3gxb mAltGX_alt_c3gxb_component ( .pll_inclk (pll_inclk), .reconfig_togxb (reconfig_togxb), .cal_blk_clk (cal_blk_clk), .reconfig_clk (reconfig_clk), .rx_analogreset (rx_analogreset), .rx_datain (rx_datain), .rx_digitalreset (rx_digitalreset), .tx_ctrlenable (tx_ctrlenable), .tx_datain (tx_datain), .tx_digitalreset (tx_digitalreset), .gxb_powerdown (gxb_powerdown), .rx_patterndetect (sub_wire0), .pll_locked (sub_wire1), .reconfig_fromgxb (sub_wire2), .rx_disperr (sub_wire3), .rx_syncstatus (sub_wire4), .rx_ctrldetect (sub_wire5), .rx_dataout (sub_wire6), .rx_errdetect (sub_wire7), .rx_rlv (sub_wire8), .tx_clkout (sub_wire9), .tx_dataout (sub_wire10)); defparam mAltGX_alt_c3gxb_component.starting_channel_number = starting_channel_number; endmodule // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX" // Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0" // Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC" // Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none" // Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "1250.0" // Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0" // Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "1250.0" // Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100" // Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000" // Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps" // Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100" // Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz" // Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "125.0" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "GIGE" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250" // Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic" // Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "1" // Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "1" // Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "1" // Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "125.0" // Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "62.5 125.0" // Retrieval info: PRIVATE: WIZ_INPUT_A STRING "1250.0" // Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps" // Retrieval info: PRIVATE: WIZ_INPUT_B STRING "125.0" // Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz" // Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0" // Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "GIGE" // Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "None" // Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0" // Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0" // Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "1250.0 Mbps" // Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "false" // Retrieval info: CONSTANT: ENABLE_PLL_INCLK_ALT_DRIVE_RX_CRU STRING "true" // Retrieval info: CONSTANT: ENABLE_PLL_INCLK_DRIVE_RX_CRU STRING "true" // Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "0" // Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false" // Retrieval info: CONSTANT: GX_CHANNEL_TYPE STRING "" // Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "125.0 MHz" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX" // Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "6" // Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "ANY" // Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none" // Retrieval info: CONSTANT: LPM_TYPE STRING "alt_c3gxb" // Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1" // Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex" // Retrieval info: CONSTANT: PLL_BANDWIDTH_TYPE STRING "Auto" // Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1" // Retrieval info: CONSTANT: PLL_INCLK_PERIOD NUMERIC "8000" // Retrieval info: CONSTANT: PLL_PFD_FB_MODE STRING "internal" // Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "0" // Retrieval info: CONSTANT: PROTOCOL STRING "gige" // Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms" // Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "0" // Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal" // Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100" // Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10" // Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false" // Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "false" // Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false" // Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE" // Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "8" // Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v" // Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "8000" // Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "basic" // Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "1250" // Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0" // Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1" // Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false" // Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false" // Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false" // Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false" // Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true" // Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "8" // Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal" // Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "10100010010101111100" // Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "10101011011010000011" // Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20" // Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "40" // Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true" // Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "8" // Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true" // Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false" // Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false" // Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false" // Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false" // Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "false" // Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false" // Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms" // Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal" // Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false" // Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "8" // Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "1" // Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v" // Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "1250" // Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0" // Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1" // Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false" // Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false" // Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "Auto" // Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "8000" // Retrieval info: CONSTANT: TX_PLL_TYPE STRING "CMU" // Retrieval info: CONSTANT: TX_SLEW_RATE STRING "medium" // Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "basic" // Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false" // Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "false" // Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false" // Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true" // Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "4" // Retrieval info: CONSTANT: equalization_setting NUMERIC "5" // Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1" // Retrieval info: CONSTANT: iqtxrxclk_allowed STRING "" // Retrieval info: CONSTANT: number_of_quads NUMERIC "1" // Retrieval info: CONSTANT: pll_divide_by STRING "1" // Retrieval info: CONSTANT: pll_multiply_by STRING "5" // Retrieval info: CONSTANT: reconfig_calibration STRING "true" // Retrieval info: CONSTANT: reconfig_fromgxb_port_width NUMERIC "5" // Retrieval info: CONSTANT: reconfig_pll_control_width NUMERIC "1" // Retrieval info: CONSTANT: reconfig_togxb_port_width NUMERIC "4" // Retrieval info: CONSTANT: rx_deskew_pattern STRING "0" // Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "1" // Retrieval info: CONSTANT: rx_enable_second_order_loop STRING "false" // Retrieval info: CONSTANT: rx_loop_1_digital_filter NUMERIC "8" // Retrieval info: CONSTANT: rx_signal_detect_loss_threshold STRING "1" // Retrieval info: CONSTANT: rx_signal_detect_valid_threshold STRING "14" // Retrieval info: CONSTANT: rx_use_external_termination STRING "false" // Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1" // Retrieval info: CONSTANT: top_module_name STRING "mAltGX" // Retrieval info: CONSTANT: tx_bitslip_enable STRING "FALSE" // Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "1" // Retrieval info: CONSTANT: tx_use_external_termination STRING "false" // Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk" // Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]" // Retrieval info: USED_PORT: pll_inclk 0 0 1 0 INPUT NODEFVAL "pll_inclk[0..0]" // Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]" // Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk" // Retrieval info: USED_PORT: reconfig_fromgxb 0 0 5 0 OUTPUT NODEFVAL "reconfig_fromgxb[4..0]" // Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 INPUT NODEFVAL "reconfig_togxb[3..0]" // Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]" // Retrieval info: USED_PORT: rx_ctrldetect 0 0 1 0 OUTPUT NODEFVAL "rx_ctrldetect[0..0]" // Retrieval info: USED_PORT: rx_datain 0 0 1 0 INPUT NODEFVAL "rx_datain[0..0]" // Retrieval info: USED_PORT: rx_dataout 0 0 8 0 OUTPUT NODEFVAL "rx_dataout[7..0]" // Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]" // Retrieval info: USED_PORT: rx_disperr 0 0 1 0 OUTPUT NODEFVAL "rx_disperr[0..0]" // Retrieval info: USED_PORT: rx_errdetect 0 0 1 0 OUTPUT NODEFVAL "rx_errdetect[0..0]" // Retrieval info: USED_PORT: rx_patterndetect 0 0 1 0 OUTPUT NODEFVAL "rx_patterndetect[0..0]" // Retrieval info: USED_PORT: rx_rlv 0 0 1 0 OUTPUT NODEFVAL "rx_rlv[0..0]" // Retrieval info: USED_PORT: rx_syncstatus 0 0 1 0 OUTPUT NODEFVAL "rx_syncstatus[0..0]" // Retrieval info: USED_PORT: tx_clkout 0 0 1 0 OUTPUT NODEFVAL "tx_clkout[0..0]" // Retrieval info: USED_PORT: tx_ctrlenable 0 0 1 0 INPUT NODEFVAL "tx_ctrlenable[0..0]" // Retrieval info: USED_PORT: tx_datain 0 0 8 0 INPUT NODEFVAL "tx_datain[7..0]" // Retrieval info: USED_PORT: tx_dataout 0 0 1 0 OUTPUT NODEFVAL "tx_dataout[0..0]" // Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]" // Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0 // Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0 // Retrieval info: CONNECT: @pll_inclk 0 0 1 0 pll_inclk 0 0 1 0 // Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0 // Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0 // Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0 // Retrieval info: CONNECT: @rx_datain 0 0 1 0 rx_datain 0 0 1 0 // Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0 // Retrieval info: CONNECT: @tx_ctrlenable 0 0 1 0 tx_ctrlenable 0 0 1 0 // Retrieval info: CONNECT: @tx_datain 0 0 8 0 tx_datain 0 0 8 0 // Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0 // Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0 // Retrieval info: CONNECT: reconfig_fromgxb 0 0 5 0 @reconfig_fromgxb 0 0 5 0 // Retrieval info: CONNECT: rx_ctrldetect 0 0 1 0 @rx_ctrldetect 0 0 1 0 // Retrieval info: CONNECT: rx_dataout 0 0 8 0 @rx_dataout 0 0 8 0 // Retrieval info: CONNECT: rx_disperr 0 0 1 0 @rx_disperr 0 0 1 0 // Retrieval info: CONNECT: rx_errdetect 0 0 1 0 @rx_errdetect 0 0 1 0 // Retrieval info: CONNECT: rx_patterndetect 0 0 1 0 @rx_patterndetect 0 0 1 0 // Retrieval info: CONNECT: rx_rlv 0 0 1 0 @rx_rlv 0 0 1 0 // Retrieval info: CONNECT: rx_syncstatus 0 0 1 0 @rx_syncstatus 0 0 1 0 // Retrieval info: CONNECT: tx_clkout 0 0 1 0 @tx_clkout 0 0 1 0 // Retrieval info: CONNECT: tx_dataout 0 0 1 0 @tx_dataout 0 0 1 0 // Retrieval info: GEN_FILE: TYPE_NORMAL mAltGX.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL mAltGX.ppf TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL mAltGX.inc FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL mAltGX.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL mAltGX.bsf FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL mAltGX_inst.v FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL mAltGX_bb.v TRUE // Retrieval info: LIB_FILE: altera_mf // Retrieval info: LIB_FILE: cycloneiv_hssi // Retrieval info: CBX_MODULE_PREFIX: ON