URL
https://opencores.org/ocsvn/sha256_hash_core/sha256_hash_core/trunk
Subversion Repositories sha256_hash_core
[/] [sha256_hash_core/] [trunk/] [syn/] [.Xil/] [PlanAhead-2528-WIN-AQV6D9G23CA/] [ngc2edif/] [_xmsgs/] [ngc2edif.xmsgs] - Rev 2
Compare with Previous | Blame | View Log
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="NetListWriters" num="298" delta="new" >No output is written to <arg fmt="%s" index="1">spi_master_atlys_top.xncf</arg>, ignored.
</msg>
<msg type="warning" file="NetListWriters" num="306" delta="new" >Signal bus <arg fmt="%s" index="1">m_rx_data_3_reg</arg><arg fmt="%s" index="2"><7 : 1></arg> on block <arg fmt="%s" index="3">spi_master_atlys_top</arg> is not reconstructed, because there are some missing bus signals.
</msg>
<msg type="warning" file="NetListWriters" num="306" delta="new" >Signal bus <arg fmt="%s" index="1">s_rx_data_3_reg</arg><arg fmt="%s" index="2"><7 : 1></arg> on block <arg fmt="%s" index="3">spi_master_atlys_top</arg> is not reconstructed, because there are some missing bus signals.
</msg>
</messages>