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[/] [sha256_hash_core/] [trunk/] [syn/] [.Xil/] [PlanAhead-2528-WIN-AQV6D9G23CA/] [ngc2edif/] [ngc2edif.log] - Rev 2
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Release 14.7 - ngc2edif P.20131013 (nt64)Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.Reading design spi_master_atlys_top.ngc ...WARNING:NetListWriters:298 - No output is written to spi_master_atlys_top.xncf,ignored.Processing design ...Preping design's networks ...Preping design's macros ...WARNING:NetListWriters:306 - Signal bus m_rx_data_3_reg<7 : 1> on blockspi_master_atlys_top is not reconstructed, because there are some missing bussignals.WARNING:NetListWriters:306 - Signal bus s_rx_data_3_reg<7 : 1> on blockspi_master_atlys_top is not reconstructed, because there are some missing bussignals.finished :PrepWriting EDIF netlist file spi_master_atlys_top.edif ...ngc2edif: Total memory usage is 80108 kilobytes