URL
https://opencores.org/ocsvn/sha256_hash_core/sha256_hash_core/trunk
Subversion Repositories sha256_hash_core
[/] [sha256_hash_core/] [trunk/] [syn/] [sha256/] [sha256.gise] - Rev 6
Go to most recent revision | Compare with Previous | Blame | View Log
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="sha256.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testbench_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testbench_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testbench_isim_beh.wdb"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testbench_stx_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1468990409" xil_pn:in_ck="7880234553005555019" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1468990409">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="gv_sha256.vhd"/>
<outfile xil_pn:name="sha256_Ki_rom.vhd"/>
<outfile xil_pn:name="sha256_Kt_rom.vhd"/>
<outfile xil_pn:name="sha256_control.vhd"/>
<outfile xil_pn:name="sha256_hash_core.vhd"/>
<outfile xil_pn:name="sha256_msg_sch.vhd"/>
<outfile xil_pn:name="sha256_padding.vhd"/>
<outfile xil_pn:name="sha256_regs.vhd"/>
<outfile xil_pn:name="sha256_test.vhd"/>
</transform>
<transform xil_pn:end_ts="1468990414" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="4434870115928851094" xil_pn:start_ts="1468990414">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1468990414" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-1902104842233773292" xil_pn:start_ts="1468990414">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1468990414" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-1109748418894572325" xil_pn:start_ts="1468990414">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1468990414" xil_pn:in_ck="7880234553005555019" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1468990414">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="gv_sha256.vhd"/>
<outfile xil_pn:name="sha256_Ki_rom.vhd"/>
<outfile xil_pn:name="sha256_Kt_rom.vhd"/>
<outfile xil_pn:name="sha256_control.vhd"/>
<outfile xil_pn:name="sha256_hash_core.vhd"/>
<outfile xil_pn:name="sha256_msg_sch.vhd"/>
<outfile xil_pn:name="sha256_padding.vhd"/>
<outfile xil_pn:name="sha256_regs.vhd"/>
<outfile xil_pn:name="sha256_test.vhd"/>
</transform>
<transform xil_pn:end_ts="1468990421" xil_pn:in_ck="7880234553005555019" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="1459423336703152140" xil_pn:start_ts="1468990414">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testbench_beh.prj"/>
<outfile xil_pn:name="testbench_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1468990422" xil_pn:in_ck="7130759491340027311" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-5414671575160791934" xil_pn:start_ts="1468990421">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testbench_isim_beh.wdb"/>
</transform>
</transforms>
</generated_project>
Go to most recent revision | Compare with Previous | Blame | View Log