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This project implements 2nd order DAC implementable in FPGA.
The converter generates 1-bit digital signal on the dout output.
You need to connect a simple RC lowpass filter to convert it into
the analog signal.
There are two implementations:
dsm2 - allows to obtain higher clock frequency, and therefore
higher oversampling ratio, but number of rising and falling
slopes in time unit depends on signal value. Therefore
you may experience nonlinear distortions if those two slopes
are not symmetrical.
dsm3 - The output of the DAC is updated once every three clock pulses.
If there is a '1' on the DAC output, the sequence '110' is generated
on the dout output. If there is a '0' on the DAC output, the sequence
'100' is generated. Therefore we always have one rising slope and one
falling slope generated in each DAC cycle.
Unfortunately this implementation accepts lower clock frequencies,
so the oversampling ratio is lower
To check DAC performance without putting it into real hardware, you can
run "make" command in the appropriate directory (it requires free tools:
ghdl, python and pylab). You'll see the spectra of the output signal
(before low pass filtering) consisting of three sinusoids.