URL
https://opencores.org/ocsvn/sincos/sincos/trunk
Subversion Repositories sincos
[/] [sincos/] [trunk/] [vhdl/] [arith/] [sincos/] [sincos.xds] - Rev 22
Compare with Previous | Blame | View Log
<?xml version="1.0" encoding="UTF-8" standalone="no" ?><DesignStrategy goal="fast sine table" strategy="register balancer" version="12.1"><Description>The Default strategy provides a balanced optimization of performance results vs. runtime. The default property values correspond to the default values of each of the underlying implementation tools. This strategy keeps all properties in an unlocked state so that you can modify the values as you wish.</Description><DeviceList devices="spartan6"/><Properties><property name="Synthesize - XST:Optimization Goal" value="Speed"/><property name="Synthesize - XST:Optimization Effort" value="High"/><property name="Synthesize - XST:Power Reduction" value="false"/><property name="Synthesize - XST:Use Synthesis Constraints File" value="true"/><property name="Synthesize - XST:Synthesis Constraints File" value=""/><property name="Synthesize - XST:Keep Hierarchy" value="Yes"/><property name="Synthesize - XST:Netlist Hierarchy" value="As Optimized"/><property name="Synthesize - XST:Global Optimization Goal" value="AllClockNets"/><property name="Synthesize - XST:Generate RTL Schematic" value="Yes"/><property name="Synthesize - XST:Read Cores" value="true"/><property name="Synthesize - XST:Cores Search Directories" value=""/><property name="Synthesize - XST:Write Timing Constraints" value="false"/><property name="Synthesize - XST:Cross Clock Analysis" value="false"/><property name="Synthesize - XST:Hierarchy Separator" value="/"/><property name="Synthesize - XST:Bus Delimiter" value="<>"/><property name="Synthesize - XST:LUT-FF Pairs Utilization Ratio" value="100"/><property name="Synthesize - XST:BRAM Utilization Ratio" value="100"/><property name="Synthesize - XST:DSP Utilization Ratio" value="100"/><property name="Synthesize - XST:Case" value="Maintain"/><property name="Synthesize - XST:Work Directory" value="/d/lib/vhdl/arith/sincos/spartan6/sincos/xst"/><property name="Synthesize - XST:HDL INI File" value=""/><property name="Synthesize - XST:Library for Verilog Sources" value=""/><property name="Synthesize - XST:Library Search Order" value=""/><property name="Synthesize - XST:Verilog Include Directories" value=""/><property name="Synthesize - XST:Generics, Parameters" value=""/><property name="Synthesize - XST:Verilog Macros" value=""/><property name="Synthesize - XST:Other XST Command Line Options" value=""/><property name="Synthesize - XST:FSM Encoding Algorithm" value="Auto"/><property name="Synthesize - XST:Safe Implementation" value="No"/><property name="Synthesize - XST:Case Implementation Style" value="None"/><property name="Synthesize - XST:FSM Style" value="LUT"/><property name="Synthesize - XST:RAM Extraction" value="true"/><property name="Synthesize - XST:RAM Style" value="Auto"/><property name="Synthesize - XST:ROM Extraction" value="true"/><property name="Synthesize - XST:ROM Style" value="Auto"/><property name="Synthesize - XST:Automatic BRAM Packing" value="false"/><property name="Synthesize - XST:Shift Register Extraction" value="true"/><property name="Synthesize - XST:Shift Register Minimum Size" value="2"/><property name="Synthesize - XST:Resource Sharing" value="true"/><property name="Synthesize - XST:Use DSP Block" value="Auto"/><property name="Synthesize - XST:Asynchronous To Synchronous" value="false"/><property name="Synthesize - XST:Add I/O Buffers" value="true"/><property name="Synthesize - XST:Max Fanout" value="100000"/><property name="Synthesize - XST:Number of Clock Buffers" value="16"/><property name="Synthesize - XST:Register Duplication" value="true"/><property name="Synthesize - XST:Equivalent Register Removal" value="true"/><property name="Synthesize - XST:Register Balancing" value="Yes"/><property name="Synthesize - XST:Move First Flip-Flop Stage" value="true"/><property name="Synthesize - XST:Move Last Flip-Flop Stage" value="true"/><property name="Synthesize - XST:Pack I/O Registers into IOBs" value="Auto"/><property name="Synthesize - XST:LUT Combining" value="Auto"/><property name="Synthesize - XST:Reduce Control Sets" value="Auto"/><property name="Synthesize - XST:Use Clock Enable" value="Auto"/><property name="Synthesize - XST:Use Synchronous Set" value="Auto"/><property name="Synthesize - XST:Use Synchronous Reset" value="Auto"/><property name="Synthesize - XST:Optimize Instantiated Primitives" value="false"/><property name="Translate:Use LOC Constraints" value="true"/><property name="Translate:Netlist Translation Type" value="Timestamp"/><property name="Translate:Macro Search Path" value=""/><property name="Translate:Create I/O Pads from Ports" value="false"/><property name="Translate:Allow Unexpanded Blocks" value="false"/><property name="Translate:User Rules File for Netlister Launcher" value=""/><property name="Translate:Allow Unmatched LOC Constraints" value="false"/><property name="Translate:Allow Unmatched Timing Group Constraints" value="false"/><property name="Translate:Other Ngdbuild Command Line Options" value=""/><property name="Map:Placer Effort Level" value="High"/><property name="Map:Placer Extra Effort" value="None"/><property name="Map:Starting Placer Cost Table (1-100)" value="1"/><property name="Map:Extra Cost Tables" value="0"/><property name="Map:Combinatorial Logic Optimization" value="false"/><property name="Map:Register Duplication" value="Off"/><property name="Map:Global Optimization" value="Off"/><property name="Map:Retiming" value="false"/><property name="Map:Equivalent Register Removal" value="true"/><property name="Map:Ignore User Timing Constraints" value="false"/><property name="Map:Timing Mode" value="Performance Evaluation"/><property name="Map:Trim Unconnected Signals" value="true"/><property name="Map:Allow Logic Optimization Across Hierarchy" value="false"/><property name="Map:Generate Detailed MAP Report" value="false"/><property name="Map:Use RLOC Constraints" value="Yes"/><property name="Map:Pack I/O Registers/Latches into IOBs" value="Off"/><property name="Map:Maximum Compression" value="false"/><property name="Map:LUT Combining" value="Off"/><property name="Map:Map Slice Logic into Unused Block RAMs" value="false"/><property name="Map:Power Reduction" value="Off"/><property name="Map:Power Activity File" value=""/><property name="Map:Enable Multi-Threading" value="Off"/><property name="Map:Other Map Command Line Options" value=""/><property name="Place & Route:Place And Route Mode" value="Route Only"/><property name="Place & Route:Place & Route Effort Level (Overall)" value="High"/><property name="Place & Route:Extra Effort (Highest PAR level only)" value="None"/><property name="Place & Route:Ignore User Timing Constraints" value="false"/><property name="Place & Route:Timing Mode" value="Performance Evaluation"/><property name="Place & Route:Generate Asynchronous Delay Report" value="false"/><property name="Place & Route:Generate Clock Region Report" value="false"/><property name="Place & Route:Generate Post-Place & Route Simulation Model" value="false"/><property name="Place & Route:Generate Post-Place & Route Power Report" value="false"/><property name="Place & Route:Power Reduction" value="false"/><property name="Place & Route:Power Activity File" value=""/><property name="Place & Route:Enable Multi-Threading" value="Off"/><property name="Place & Route:Other Place & Route Command Line Options" value=""/><property name="Generate Programming File:Run Design Rules Checker (DRC)" value="true"/><property name="Generate Programming File:Create Bit File" value="true"/><property name="Generate Programming File:Create Binary Configuration File" value="false"/><property name="Generate Programming File:Create ASCII Configuration File" value="false"/><property name="Generate Programming File:Create IEEE 1532 Configuration File" value="false"/><property name="Generate Programming File:Enable BitStream Compression" value="false"/><property name="Generate Programming File:Enable Debugging of Serial Mode BitStream" value="false"/><property name="Generate Programming File:Enable Cyclic Redundancy Checking (CRC)" value="true"/><property name="Generate Programming File:Retry Configuration if CRC Error Occurs" value="false"/><property name="Generate Programming File:Other Bitgen Command Line Options" value=""/><property name="Generate Programming File:Configuration Rate" value="2"/><property name="Generate Programming File:Configuration Pin Program" value="Pull Up"/><property name="Generate Programming File:Configuration Pin Done" value="Pull Up"/><property name="Generate Programming File:JTAG Pin TCK" value="Pull Up"/><property name="Generate Programming File:JTAG Pin TDI" value="Pull Up"/><property name="Generate Programming File:JTAG Pin TDO" value="Pull Up"/><property name="Generate Programming File:JTAG Pin TMS" value="Pull Up"/><property name="Generate Programming File:Unused IOB Pins" value="Pull Down"/><property name="Generate Programming File:UserID Code (8 Digit Hexadecimal)" value="0xFFFFFFFF"/><property name="Generate Programming File:Enable External Master Clock" value="false"/><property name="Generate Programming File:Setup External Master Clock Division" value="1"/><property name="Generate Programming File:Set SPI Configuration Bus Width" value="1"/><property name="Generate Programming File:Watchdog Timer Value" value="0xFFFF"/><property name="Generate Programming File:Place MultiBoot Settings into Bitstream" value="false"/><property name="Generate Programming File:MultiBoot: Starting Address for Next Configuration" value="0x00000000"/><property name="Generate Programming File:MultiBoot: Use New Mode for Next Configuration" value="true"/><property name="Generate Programming File:MultiBoot: Next Configuration Mode" value="001"/><property name="Generate Programming File:MultiBoot: Starting Address for Golden Configuration" value="0x00000000"/><property name="Generate Programming File:MultiBoot: User-Defined Register for Failsafe Scheme" value="0x0000"/><property name="Generate Programming File:FPGA Start-Up Clock" value="CCLK"/><property name="Generate Programming File:Enable Internal Done Pipe" value="false"/><property name="Generate Programming File:Done (Output Events)" value="Default (4)"/><property name="Generate Programming File:Enable Outputs (Output Events)" value="Default (5)"/><property name="Generate Programming File:Release Write Enable (Output Events)" value="Default (6)"/><property name="Generate Programming File:Wait for DCM and PLL Lock (Output Events)" value="Default (NoWait)"/><property name="Generate Programming File:Drive Done Pin High" value="false"/><property name="Generate Programming File:Security" value="Enable Readback and Reconfiguration"/><property name="Generate Programming File:Create ReadBack Data Files" value="false"/><property name="Generate Programming File:Allow SelectMAP Pins to Persist" value="false"/><property name="Generate Programming File:Create Logic Allocation File" value="false"/><property name="Generate Programming File:Create Mask File" value="false"/><property name="Generate Programming File:Encrypt Bitstream" value="false"/><property name="Generate Programming File:Encrypt Key Select" value="BBRAM"/><property name="Generate Programming File:AES Key (Hex String)" value=""/><property name="Generate Programming File:Input Encryption Key File" value=""/><property name="Generate Programming File:AES Initial Vector" value=""/><property name="Generate Programming File:Enable Suspend/Wake Global Set/Reset" value="false"/><property name="Generate Programming File:Drive Awake Pin During Suspend/Wake Sequence" value="false"/><property name="Generate Programming File:Wakeup Clock" value="Startup Clock"/><property name="Generate Programming File:GWE Cycle During Suspend/Wakeup Sequence" value="5"/><property name="Generate Programming File:GTS Cycle During Suspend/Wakeup Sequence" value="4"/><property name="Generate Programming File:Enable Multi-Pin Wake-Up Suspend Mode" value="false"/><property name="Generate Programming File:Mask Pins for Multi-Pin Wake-Up Suspend Mode" value="0x00"/><property name="Generate Post-Place & Route Static Timing:Place And Route Mode" value="Route Only"/><property name="Generate Post-Place & Route Static Timing:Place & Route Effort Level (Overall)" value="High"/><property name="Generate Post-Place & Route Static Timing:Extra Effort (Highest PAR level only)" value="None"/><property name="Generate Post-Place & Route Static Timing:Ignore User Timing Constraints" value="false"/><property name="Generate Post-Place & Route Static Timing:Timing Mode" value="Performance Evaluation"/><property name="Generate Post-Place & Route Static Timing:Generate Asynchronous Delay Report" value="false"/><property name="Generate Post-Place & Route Static Timing:Generate Clock Region Report" value="false"/><property name="Generate Post-Place & Route Static Timing:Generate Post-Place & Route Simulation Model" value="false"/><property name="Generate Post-Place & Route Static Timing:Generate Post-Place & Route Power Report" value="false"/><property name="Generate Post-Place & Route Static Timing:Power Reduction" value="false"/><property name="Generate Post-Place & Route Static Timing:Power Activity File" value=""/><property name="Generate Post-Place & Route Static Timing:Enable Multi-Threading" value="Off"/><property name="Generate Post-Place & Route Static Timing:Other Place & Route Command Line Options" value=""/><property name="Generate Power Data:Produce Verbose Report" value="false"/><property name="Generate Power Data:Produce Advanced Verbose Report" value="false"/><property name="Generate Power Data:Maximum Number of Lines in Report" value="1000"/><property name="Generate Power Data:Load Setting File" value=""/><property name="Generate Power Data:Setting Output File" value=""/><property name="Generate Power Data:Load Simulation File" value="Default"/><property name="Generate Power Data:Load Physical Constraints File" value="Default"/><property name="Generate Power Data:Input TCL Command Script" value=""/><property name="Generate Power Data:Other XPWR Command Line Options" value=""/></Properties></DesignStrategy>