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URL https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk

Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [DisplayDriverwDecoder.ldf] - Rev 9

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<?xml version="1.0" encoding="UTF-8"?>
<BaliProject version="3.2" title="DisplayDriverwDecoder" device="LFE5UM5G-45F-8BG381C" default_implementation="impl1">
    <Options>
        <Option name="HDL type" value="VHDL"/>
    </Options>
    <Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
        <Options def_top="display_driver_wrapper"/>
        <Source name="../Sources/ascii_decoder.vhd" type="VHDL" type_short="VHDL">
            <Options/>
        </Source>
        <Source name="../Sources/display_driver_w_decoder.vhd" type="VHDL" type_short="VHDL">
            <Options/>
        </Source>
        <Source name="../Sources/display_driver_wrapper.vhd" type="VHDL" type_short="VHDL">
            <Options top_module="display_driver_wrapper"/>
        </Source>
        <Source name="../Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.vhd" type="VHDL" type_short="VHDL">
            <Options/>
        </Source>
        <Source name="DisplayDriverwDecoder.lpf" type="Logic Preference" type_short="LPF">
            <Options/>
        </Source>
        <Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
            <Options/>
        </Source>
    </Implementation>
    <Strategy name="Strategy1" file="DisplayDriverwDecoder1.sty"/>
</BaliProject>

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