URL
https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk
Subversion Repositories single-14-segment-display-driver-w-decoder
[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [DisplayDriverwDecoder_impl1.lsedata] - Rev 5
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<top name = "DisplayDriverWrapper" library = "work" arch = "RTL" entry = "VHDL">
<clocks>
</clocks>
<!--
//=============================================================
// Number of Clocks processed: 0
//
// If a clock cannot be found in the top level pins section,
// that means it is an internal clock.
//
//=============================================================
-->
<library name = "work">
<unit name = "DisplayDriverWrapper">
<!--
Top Level Pins: 18
-->
<pins>
<pitem name = "clk" direction = "in" />
<pitem name = "reset" direction = "in" />
<pitem name = "button" direction = "in" />
<pitem name = "disp_data[13]" direction = "out" />
<pitem name = "disp_data[12]" direction = "out" />
<pitem name = "disp_data[11]" direction = "out" />
<pitem name = "disp_data[10]" direction = "out" />
<pitem name = "disp_data[9]" direction = "out" />
<pitem name = "disp_data[8]" direction = "out" />
<pitem name = "disp_data[7]" direction = "out" />
<pitem name = "disp_data[6]" direction = "out" />
<pitem name = "disp_data[5]" direction = "out" />
<pitem name = "disp_data[4]" direction = "out" />
<pitem name = "disp_data[3]" direction = "out" />
<pitem name = "disp_data[2]" direction = "out" />
<pitem name = "disp_data[1]" direction = "out" />
<pitem name = "disp_data[0]" direction = "out" />
<pitem name = "disp_sel" direction = "out" />
</pins>
<!--
Instances in netlist: 1
-->
<instance name = "DDwD_Top" />
<!--
Views in design "DisplayDriverWrapper": 1
-->
<views>
<view name = "DisplayDriverwDecoder_Top" />
</views>
</unit>
</library>
</top>