Subversion Repositories single-14-segment-display-driver-w-decoder

PAR: Place And Route Diamond (64-bit) 3.8.0.115.3.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation,  All rights reserved.
Fri Jan 13 00:54:53 2017

C:/lscc/diamond/3.8_x64/ispfpga\bin\nt64\par -f DisplayDriverwDecoder_impl1.p2t
DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.dir
DisplayDriverwDecoder_impl1.prf -gui -msgset
C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml


Preference file: DisplayDriverwDecoder_impl1.prf.

Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
----------   --------     -----        ------       -----------  -----------  ----         ------
5_1   *      0            -            -            -            -            06           Complete


* : Design saved.

Total (real) run time for 1-seed: 6 secs 

par done!

Lattice Place and Route Report for Design "DisplayDriverwDecoder_impl1_map.ncd"
Fri Jan 13 00:54:53 2017

PAR: Place And Route Diamond (64-bit) 3.8.0.115.3.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml -exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.dir/5_1.ncd DisplayDriverwDecoder_impl1.prf
Preference file: DisplayDriverwDecoder_impl1.prf.
Placement level-cost: 5-1.
Routing Iterations: 6

Loading design for application par from file DisplayDriverwDecoder_impl1_map.ncd.
Design name: DisplayDriverWrapper
NCD version: 3.3
Vendor:      LATTICE
Device:      LFE5UM5G-45F
Package:     CABGA381
Performance: 8
Loading device for application par from file 'sa5p45m.nph' in environment: C:/lscc/diamond/3.8_x64/ispfpga.
Package Status:                     Final          Version 1.36.
Performance Hardware Data Status:   Final          Version 50.1.
License checked out.


Ignore Preference Error(s):  True
Device utilization summary:

   PIO (prelim)      16/245           6% used
                     16/203           7% bonded

   SLICE              0/21924         0% used



Number of Signals: 0
Number of Connections: 0

Pin Constraint Summary:
   16 out of 16 pins locked (100% locked).


No signal is selected as Global Set/Reset.
Starting Placer Phase 0.

Finished Placer Phase 0.  REAL time: 5 secs 

Starting Placer Phase 1.

Placer score = 0.
Finished Placer Phase 1.  REAL time: 5 secs 

Starting Placer Phase 2.
.
Placer score =  0
Finished Placer Phase 2.  REAL time: 5 secs 


------------------ Clock Report ------------------

Global Clock Resources:
  CLK_PIN    : 0 out of 12 (0%)
  GR_PCLK    : 0 out of 12 (0%)
  PLL        : 0 out of 4 (0%)
  DCS        : 0 out of 2 (0%)
  DCC        : 0 out of 60 (0%)
  CLKDIV     : 0 out of 4 (0%)

Quadrant TL Clocks:

  PRIMARY  : 0 out of 16 (0%)

Quadrant TR Clocks:

  PRIMARY  : 0 out of 16 (0%)

Quadrant BL Clocks:

  PRIMARY  : 0 out of 16 (0%)

Quadrant BR Clocks:

  PRIMARY  : 0 out of 16 (0%)

Edge Clocks:

  No edge clock selected.


--------------- End of Clock Report ---------------


+
I/O Usage Summary (final):
   16 out of 245 (6.5%) PIO sites used.
   16 out of 203 (7.9%) bonded PIO sites used.
   Number of PIO comps: 16; differential: 0.
   Number of Vref pins used: 0.

I/O Bank Usage Summary:
+----------+----------------+------------+------------+------------+
| I/O Bank | Usage          | Bank Vccio | Bank Vref1 | Bank Vref2 |
+----------+----------------+------------+------------+------------+
| 0        | 0 / 27 (  0%)  | -          | -          | -          |
| 1        | 0 / 33 (  0%)  | -          | -          | -          |
| 2        | 0 / 32 (  0%)  | -          | -          | -          |
| 3        | 14 / 33 ( 42%) | 2.5V       | -          | -          |
| 6        | 1 / 33 (  3%)  | 2.5V       | -          | -          |
| 7        | 0 / 32 (  0%)  | -          | -          | -          |
| 8        | 1 / 13 (  7%)  | 2.5V       | -          | -          |
+----------+----------------+------------+------------+------------+

Total placer CPU time: 3 secs 

Dumping design to file DisplayDriverwDecoder_impl1.dir/5_1.ncd.

INFO - par: The routing stage will be skipped since the design contains no signals and/or connections.
Timing score: 0 

Dumping design to file DisplayDriverwDecoder_impl1.dir/5_1.ncd.


All signals are completely routed.


PAR_SUMMARY::Run status = completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst  slack<setup/<ns>> = <n/a>
PAR_SUMMARY::Timing score<setup/<ns>> = <n/a>
PAR_SUMMARY::Worst  slack<hold /<ns>> = <n/a>
PAR_SUMMARY::Timing score<hold /<ns>> = <n/a>
PAR_SUMMARY::Number of errors = 0

Total CPU  time to completion: 4 secs 
Total REAL time to completion: 6 secs 

par done!

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation,  All rights reserved.