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https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk
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[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [DisplayDriverwDecoder_impl1.prf] - Rev 9
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SCHEMATIC START ;# map: version Diamond (64-bit) 3.8.0.115.3 -- WARNING: Map write only section -- Wed Jan 18 01:08:24 2017SYSCONFIG SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE BACKGROUND_RECONFIG=OFF DONE_EX=OFF DONE_OD=ON DONE_PULL=ON MCCLK_FREQ=2.4 TRANSFR=OFF CONFIG_IOVOLTAGE=2.5 CONFIG_SECURE=OFF WAKE_UP=21 COMPRESS_CONFIG=OFF CONFIG_MODE=JTAG ;LOCATE COMP "disp_data_q[0]" SITE "M20" ;LOCATE COMP "clk" SITE "P3" ;LOCATE COMP "disp_data_q[14]" SITE "U1" ;LOCATE COMP "disp_data_q[13]" SITE "R16" ;LOCATE COMP "disp_data_q[12]" SITE "P16" ;LOCATE COMP "disp_data_q[11]" SITE "N17" ;LOCATE COMP "disp_data_q[10]" SITE "N18" ;LOCATE COMP "disp_data_q[9]" SITE "M17" ;LOCATE COMP "disp_data_q[8]" SITE "N16" ;LOCATE COMP "disp_data_q[7]" SITE "P17" ;LOCATE COMP "disp_data_q[6]" SITE "R17" ;LOCATE COMP "disp_data_q[5]" SITE "M18" ;LOCATE COMP "disp_data_q[4]" SITE "L17" ;LOCATE COMP "disp_data_q[3]" SITE "L16" ;LOCATE COMP "disp_data_q[2]" SITE "M19" ;LOCATE COMP "disp_data_q[1]" SITE "L18" ;LOCATE COMP "button" SITE "T1" ;LOCATE COMP "n_rst" SITE "K20" ;SCHEMATIC END ;BLOCK RESETPATHS ;BLOCK ASYNCPATHS ;COMMERCIAL ;// No timing preferences found. TRCE invokes auto-generation of timing preferences// Section AutogenFREQUENCY NET "clk_c" 369.959 MHz ;// End Section Autogen