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[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [DisplayDriverwDecoder_impl1.srf] - Rev 9
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#Build: Synplify Pro L-2016.03L-1, Build 097R, Jul 4 2016#install: C:\lscc\diamond\3.8_x64\synpbase#OS: Windows 8 6.2#Hostname: DESKTOP-1AUKF7V# Wed Jan 18 01:08:13 2017#Implementation: impl1Synopsys HDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016@N|Running in 64-bit modeCopyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.Synopsys VHDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016@N|Running in 64-bit modeCopyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.@N: CD720 :"C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns@N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:28|Top entity is set to display_driver_wrapper.File C:\lscc\diamond\3.8_x64\synpbase\lib\lucent\ecp5um.vhd changed - recompilingFile C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd changed - recompilingFile C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd changed - recompilingFile C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd changed - recompilingVHDL syntax check successful!File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd changed - recompiling@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:28|Synthesizing work.display_driver_wrapper.arch.@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":17:7:17:30|Synthesizing work.display_driver_w_decoder.display_driver_w_decoder_arch.@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":42:11:42:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd":15:7:15:19|Synthesizing work.ascii_decoder.arch.@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\decoder_table_dist_rom_impl\decoder_table_dist_rom\decoder_table_dist_rom.vhd":12:7:12:28|Synthesizing work.decoder_table_dist_rom.structure.@N: CD630 :"C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd":801:10:801:18|Synthesizing work.rom128x1a.syn_black_box.Post processing for work.rom128x1a.syn_black_boxPost processing for work.decoder_table_dist_rom.structurePost processing for work.ascii_decoder.archPost processing for work.display_driver_w_decoder.display_driver_w_decoder_archPost processing for work.display_driver_wrapper.arch@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd":17:8:17:10|Input clk is unused.@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd":18:8:18:12|Input reset is unused.@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":23:8:23:12|Input wr_en is unused.At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)Process took 0h:00m:01s realtime, 0h:00m:01s cputimeProcess completed successfully.# Wed Jan 18 01:08:13 2017###########################################################]Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016@N|Running in 64-bit modeFile C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\layer0.srs changed - recompilingAt syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)Process took 0h:00m:01s realtime, 0h:00m:01s cputimeProcess completed successfully.# Wed Jan 18 01:08:13 2017###########################################################]@ENDAt c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)Process took 0h:00m:01s realtime, 0h:00m:01s cputimeProcess completed successfully.# Wed Jan 18 01:08:13 2017###########################################################]Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016@N|Running in 64-bit modeFile C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_comp.srs changed - recompilingAt syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)Process took 0h:00m:01s realtime, 0h:00m:01s cputimeProcess completed successfully.# Wed Jan 18 01:08:14 2017###########################################################]Pre-mapping ReportSynopsys Lattice Technology Pre-mapping, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.Product Version L-2016.03L-1Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)@A: MF827 |No constraint file specified.@L: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1_scck.rptPrinting clock summary report in "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1_scck.rpt" file@N: MF248 |Running in 64-bit mode.@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)ICG Latch Removal Summary:Number of ICG latches removed: 0Number of ICG latches not removed: 0syn_allowed_resources : blockrams=108 set on top level netlist display_driver_wrapperFinished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)Clock Summary*****************Start Requested Requested Clock Clock ClockClock Frequency Period Type Group Load-------------------------------------------------------------------------------------------------------------------------------------------------------------display_driver_wrapper|bttn_state_derived_clock 1.0 MHz 1000.000 derived (from display_driver_wrapper|clk) Autoconstr_clkgroup_0 8display_driver_wrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 5=============================================================================================================================================================@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd":52:8:52:9|Found inferred clock display_driver_wrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.Finished Pre Mapping Phase.Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)NoneNoneFinished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)Pre-mapping successful!At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB)Process took 0h:00m:01s realtime, 0h:00m:01s cputime# Wed Jan 18 01:08:15 2017###########################################################]Map & Optimize ReportSynopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.Product Version L-2016.03L-1Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)@N: MF248 |Running in 64-bit mode.@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)Available hyper_sources - for debug and ip modelsNone Found@N: MT206 |Auto Constrain mode is enabledFinished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)@N:"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd":74:8:74:9|Found counter in view:work.display_driver_wrapper(arch) inst symbol_scan_cntr[7:0]Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)Pass CPU time Worst Slack Luts / Registers------------------------------------------------------------1 0h:00m:00s -0.76ns 6 / 132 0h:00m:00s -0.76ns 6 / 133 0h:00m:00s -0.62ns 7 / 134 0h:00m:00s -0.58ns 6 / 13Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)@N: MT611 :|Automatically generated clock display_driver_wrapper|bttn_state_derived_clock is not used and is being removed@S |Clock Optimization Summary#### START OF CLOCK OPTIMIZATION REPORT #####[1 non-gated/non-generated clock tree(s) driving 13 clock pin(s) of sequential element(s)0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)8 instances converted, 0 sequential instances remain driven by gated/generated clocks=========================== Non-Gated/Non-Generated Clocks ============================Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance---------------------------------------------------------------------------------------@K:CKID0001 clk port 13 bttn_state=======================================================================================##### END OF CLOCK OPTIMIZATION REPORT ######]Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 141MB)Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_m.srmFinished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 139MB peak: 141MB)Writing EDIF Netlist and constraint files@N: FX1056 |Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.ediL-2016.03L-1@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pFFinished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)@W: MT420 |Found inferred clock display_driver_wrapper|clk with period 2.30ns. Please declare a user-defined clock on object "p:clk"##### START OF TIMING REPORT #####[# Timing Report written on Wed Jan 18 01:08:17 2017#Top view: display_driver_wrapperRequested Frequency: 433.9 MHzWire load mode: topPaths requested: 5Constraint File(s):@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.Performance Summary*******************Worst slack in design: -0.407Requested Estimated Requested Estimated Clock ClockStarting Clock Frequency Frequency Period Period Slack Type Group------------------------------------------------------------------------------------------------------------------------------------display_driver_wrapper|clk 433.9 MHz 368.8 MHz 2.305 2.712 -0.407 inferred Autoconstr_clkgroup_0====================================================================================================================================Clock Relationships*******************Clocks | rise to rise | fall to fall | rise to fall | fall to rise-----------------------------------------------------------------------------------------------------------------------------------------------Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack-----------------------------------------------------------------------------------------------------------------------------------------------display_driver_wrapper|clk display_driver_wrapper|clk | 2.305 -0.407 | No paths - | No paths - | No paths -===============================================================================================================================================Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.Interface Information*********************No IO constraint found====================================Detailed Report for Clock: display_driver_wrapper|clk====================================Starting Points with Worst Slack********************************Starting ArrivalInstance Reference Type Pin Net Time SlackClock---------------------------------------------------------------------------------------------------------------------symbol_scan_cntr[0] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[0] 0.933 -0.407symbol_scan_cntr[1] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[1] 0.933 -0.348symbol_scan_cntr[2] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[2] 0.933 -0.348symbol_scan_cntr[3] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[3] 0.933 -0.289symbol_scan_cntr[4] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[4] 0.933 -0.289symbol_scan_cntr[5] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[5] 0.933 -0.230symbol_scan_cntr[6] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[6] 0.933 -0.230bttn_state_fifo[3] display_driver_wrapper|clk FD1S3JX Q bttn_state_fifo[3] 0.798 0.123bttn_state display_driver_wrapper|clk FD1S3AX Q bttn_state_i 0.753 0.168bttn_state_fifo[1] display_driver_wrapper|clk FD1S3JX Q bttn_state_fifo[1] 0.838 0.606=====================================================================================================================Ending Points with Worst Slack******************************Starting RequiredInstance Reference Type Pin Net Time SlackClock----------------------------------------------------------------------------------------------------------------------------------symbol_scan_cntr[7] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[7] 2.094 -0.407symbol_scan_cntr[5] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[5] 2.094 -0.348symbol_scan_cntr[6] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[6] 2.094 -0.348symbol_scan_cntr[3] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[3] 2.094 -0.289symbol_scan_cntr[4] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[4] 2.094 -0.289symbol_scan_cntr[1] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[1] 2.094 -0.230symbol_scan_cntr[2] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[2] 2.094 -0.230symbol_scan_cntr[0] display_driver_wrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123symbol_scan_cntr[1] display_driver_wrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123symbol_scan_cntr[2] display_driver_wrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123==================================================================================================================================Worst Path Information***********************Path information for path number 1:Requested Period: 2.305- Setup time: 0.211+ Clock delay at ending point: 0.000 (ideal)= Required time: 2.094- Propagation time: 2.501- Clock delay at starting point: 0.000 (ideal)= Slack (critical) : -0.407Number of logic level(s): 5Starting point: symbol_scan_cntr[0] / QEnding point: symbol_scan_cntr[7] / DThe start point is clocked by display_driver_wrapper|clk [rising] on pin CKThe end point is clocked by display_driver_wrapper|clk [rising] on pin CKInstance / Net Pin Pin Arrival No. ofName Type Name Dir Delay Time Fan Out(s)-------------------------------------------------------------------------------------------symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -symbol_scan_cntr[0] Net - - - - 15symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -symbol_scan_cntr_cry[0] Net - - - - 1symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -symbol_scan_cntr_cry[2] Net - - - - 1symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -symbol_scan_cntr_cry[4] Net - - - - 1symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.894 -symbol_scan_cntr_cry[6] Net - - - - 1symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.894 -symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.501 -symbol_scan_cntr_s[7] Net - - - - 1symbol_scan_cntr[7] FD1P3DX D In 0.000 2.501 -===========================================================================================Path information for path number 2:Requested Period: 2.305- Setup time: 0.211+ Clock delay at ending point: 0.000 (ideal)= Required time: 2.094- Propagation time: 2.442- Clock delay at starting point: 0.000 (ideal)= Slack (non-critical) : -0.348Number of logic level(s): 4Starting point: symbol_scan_cntr[1] / QEnding point: symbol_scan_cntr[7] / DThe start point is clocked by display_driver_wrapper|clk [rising] on pin CKThe end point is clocked by display_driver_wrapper|clk [rising] on pin CKInstance / Net Pin Pin Arrival No. ofName Type Name Dir Delay Time Fan Out(s)-------------------------------------------------------------------------------------------symbol_scan_cntr[1] FD1P3DX Q Out 0.933 0.933 -symbol_scan_cntr[1] Net - - - - 15symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -symbol_scan_cntr_cry[2] Net - - - - 1symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -symbol_scan_cntr_cry[4] Net - - - - 1symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -symbol_scan_cntr_cry[6] Net - - - - 1symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -symbol_scan_cntr_s[7] Net - - - - 1symbol_scan_cntr[7] FD1P3DX D In 0.000 2.442 -===========================================================================================Path information for path number 3:Requested Period: 2.305- Setup time: 0.211+ Clock delay at ending point: 0.000 (ideal)= Required time: 2.094- Propagation time: 2.442- Clock delay at starting point: 0.000 (ideal)= Slack (non-critical) : -0.348Number of logic level(s): 4Starting point: symbol_scan_cntr[2] / QEnding point: symbol_scan_cntr[7] / DThe start point is clocked by display_driver_wrapper|clk [rising] on pin CKThe end point is clocked by display_driver_wrapper|clk [rising] on pin CKInstance / Net Pin Pin Arrival No. ofName Type Name Dir Delay Time Fan Out(s)-------------------------------------------------------------------------------------------symbol_scan_cntr[2] FD1P3DX Q Out 0.933 0.933 -symbol_scan_cntr[2] Net - - - - 15symbol_scan_cntr_cry_0[1] CCU2C A1 In 0.000 0.933 -symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -symbol_scan_cntr_cry[2] Net - - - - 1symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -symbol_scan_cntr_cry[4] Net - - - - 1symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -symbol_scan_cntr_cry[6] Net - - - - 1symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -symbol_scan_cntr_s[7] Net - - - - 1symbol_scan_cntr[7] FD1P3DX D In 0.000 2.442 -===========================================================================================Path information for path number 4:Requested Period: 2.305- Setup time: 0.211+ Clock delay at ending point: 0.000 (ideal)= Required time: 2.094- Propagation time: 2.442- Clock delay at starting point: 0.000 (ideal)= Slack (non-critical) : -0.348Number of logic level(s): 4Starting point: symbol_scan_cntr[0] / QEnding point: symbol_scan_cntr[5] / DThe start point is clocked by display_driver_wrapper|clk [rising] on pin CKThe end point is clocked by display_driver_wrapper|clk [rising] on pin CKInstance / Net Pin Pin Arrival No. ofName Type Name Dir Delay Time Fan Out(s)-------------------------------------------------------------------------------------------symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -symbol_scan_cntr[0] Net - - - - 15symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -symbol_scan_cntr_cry[0] Net - - - - 1symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -symbol_scan_cntr_cry[2] Net - - - - 1symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -symbol_scan_cntr_cry[4] Net - - - - 1symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -symbol_scan_cntr_cry_0[5] CCU2C S0 Out 0.607 2.442 -symbol_scan_cntr_s[5] Net - - - - 1symbol_scan_cntr[5] FD1P3DX D In 0.000 2.442 -===========================================================================================Path information for path number 5:Requested Period: 2.305- Setup time: 0.211+ Clock delay at ending point: 0.000 (ideal)= Required time: 2.094- Propagation time: 2.442- Clock delay at starting point: 0.000 (ideal)= Slack (non-critical) : -0.348Number of logic level(s): 4Starting point: symbol_scan_cntr[0] / QEnding point: symbol_scan_cntr[6] / DThe start point is clocked by display_driver_wrapper|clk [rising] on pin CKThe end point is clocked by display_driver_wrapper|clk [rising] on pin CKInstance / Net Pin Pin Arrival No. ofName Type Name Dir Delay Time Fan Out(s)-------------------------------------------------------------------------------------------symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -symbol_scan_cntr[0] Net - - - - 15symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -symbol_scan_cntr_cry[0] Net - - - - 1symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -symbol_scan_cntr_cry[2] Net - - - - 1symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -symbol_scan_cntr_cry[4] Net - - - - 1symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -symbol_scan_cntr_cry_0[5] CCU2C S1 Out 0.607 2.442 -symbol_scan_cntr_s[6] Net - - - - 1symbol_scan_cntr[6] FD1P3DX D In 0.000 2.442 -===========================================================================================##### END OF TIMING REPORT #####]Constraints that could not be appliedNoneFinished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)---------------------------------------Resource Usage ReportPart: lfe5um5g_45f-8Register bits: 13 of 43848 (0%)PIC Latch: 0I/O cells: 18Details:CCU2C: 5FD1P3DX: 8FD1S3AX: 1FD1S3JX: 3GSR: 1IB: 3IFS1P3JX: 1INV: 2OB: 15ORCALUT4: 4PUR: 1ROM128X1A: 14VHI: 1VLO: 1Mapper successful!At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB)Process took 0h:00m:01s realtime, 0h:00m:01s cputime# Wed Jan 18 01:08:17 2017###########################################################]