OpenCores
URL https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk

Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [DisplayDriverwDecoder_impl1_cck.rpt] - Rev 9

Compare with Previous | Blame | View Log

# Synopsys Constraint Checker, version maplat, Build 1498R, built Jul  5 2016
# Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

# Written on Wed Jan 18 01:08:15 2017


##### DESIGN INFO #######################################################

Top View:                "display_driver_wrapper"
Constraint File(s):      (none)




##### SUMMARY ############################################################

Found 0 issues in 0 out of 0 constraints


##### DETAILS ############################################################



Clock Relationships
*******************

Starting                                            Ending                                              |     rise to rise     |     fall to fall     |     rise to fall     |     fall to rise                     
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
display_driver_wrapper|clk                          display_driver_wrapper|clk                          |     1000.000         |     No paths         |     No paths         |     No paths                         
display_driver_wrapper|bttn_state_derived_clock     display_driver_wrapper|bttn_state_derived_clock     |     1000.000         |     No paths         |     No paths         |     No paths                         
===================================================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.


Unconstrained Start/End Points
******************************

p:button
p:disp_data_q[0]
p:disp_data_q[1]
p:disp_data_q[2]
p:disp_data_q[3]
p:disp_data_q[4]
p:disp_data_q[5]
p:disp_data_q[6]
p:disp_data_q[7]
p:disp_data_q[8]
p:disp_data_q[9]
p:disp_data_q[10]
p:disp_data_q[11]
p:disp_data_q[12]
p:disp_data_q[13]
p:disp_data_q[14]
p:n_rst


Inapplicable constraints
************************

(none)


Applicable constraints with issues
**********************************

(none)


Constraints with matching wildcard expressions
**********************************************

(none)


Library Report
**************


# End of Constraint Checker Report

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.