URL
https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk
Subversion Repositories single-14-segment-display-driver-w-decoder
[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [DisplayDriverwDecoder_impl1_scck.rpt] - Rev 9
Compare with Previous | Blame | View Log
# Synopsys Constraint Checker(syntax only), version maplat, Build 1498R, built Jul 5 2016# Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.# Written on Wed Jan 18 01:08:15 2017##### DESIGN INFO #######################################################Top View: "display_driver_wrapper"Constraint File(s): (none)#Run constraint checker to find more issues with constraints.#########################################################################No issues found in constraint syntax.Clock Summary*************Start Requested Requested Clock Clock ClockClock Frequency Period Type Group Load-------------------------------------------------------------------------------------------------------------------------------------------------------------display_driver_wrapper|bttn_state_derived_clock 1.0 MHz 1000.000 derived (from display_driver_wrapper|clk) Autoconstr_clkgroup_0 8display_driver_wrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 5=============================================================================================================================================================