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URL https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk

Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [DisplayDriverwDecoder_impl1_synplify.lpf] - Rev 9

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#
# Logical Preferences generated for Lattice by Synplify maplat, Build 1498R.
#

# Period Constraints 
#FREQUENCY PORT "clk" 433.9 MHz;


# Output Constraints 

# Input Constraints 

# Point-to-point Delay Constraints 



# Block Path Constraints 

BLOCK ASYNCPATHS;

# End of generated Logical Preferences.

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