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[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [synlog/] [DisplayDriverwDecoder_impl1_fpga_mapper.srr] - Rev 6
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Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.Product Version L-2016.03L-1Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)@N: MF248 |Running in 64-bit mode.@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)Available hyper_sources - for debug and ip modelsNone Found@N: MT206 |Auto Constrain mode is enabledFinished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)@N:"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Found counter in view:work.DisplayDriverWrapper(arch) inst symbol_scan_cntr[7:0]Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)Pass CPU time Worst Slack Luts / Registers------------------------------------------------------------1 0h:00m:00s -0.70ns 1 / 82 0h:00m:00s -0.70ns 1 / 8@N: FX271 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Replicating instance symbol_scan_cntr[0] (in view: work.DisplayDriverWrapper(arch)) with 15 loads 1 time to improve timing.Timing driven replication reportAdded 1 Registers via timing driven replicationAdded 0 LUTs via timing driven replication3 0h:00m:00s -0.64ns 1 / 94 0h:00m:00s -0.64ns 1 / 9Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)@S |Clock Optimization Summary#### START OF CLOCK OPTIMIZATION REPORT #####[1 non-gated/non-generated clock tree(s) driving 9 clock pin(s) of sequential element(s)0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)0 instances converted, 0 sequential instances remain driven by gated/generated clocks============================= Non-Gated/Non-Generated Clocks ==============================Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance-------------------------------------------------------------------------------------------@K:CKID0001 button port 9 symbol_scan_cntr[0]===========================================================================================##### END OF CLOCK OPTIMIZATION REPORT ######]Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 141MB)Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_m.srmFinished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)Writing EDIF Netlist and constraint files@N: FX1056 |Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.ediL-2016.03L-1@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pFFinished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)@W: MT420 |Found inferred clock DisplayDriverWrapper|button with period 2.25ns. Please declare a user-defined clock on object "p:button"##### START OF TIMING REPORT #####[# Timing Report written on Tue Jan 17 01:19:13 2017#Top view: DisplayDriverWrapperRequested Frequency: 443.5 MHzWire load mode: topPaths requested: 5Constraint File(s):@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.Performance Summary*******************Worst slack in design: -0.398Requested Estimated Requested Estimated Clock ClockStarting Clock Frequency Frequency Period Period Slack Type Group-------------------------------------------------------------------------------------------------------------------------------------DisplayDriverWrapper|button 443.5 MHz 377.0 MHz 2.255 2.652 -0.398 inferred Autoconstr_clkgroup_0=====================================================================================================================================Clock Relationships*******************Clocks | rise to rise | fall to fall | rise to fall | fall to rise-------------------------------------------------------------------------------------------------------------------------------------------------Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack-------------------------------------------------------------------------------------------------------------------------------------------------DisplayDriverWrapper|button DisplayDriverWrapper|button | 2.255 -0.398 | No paths - | No paths - | No paths -=================================================================================================================================================Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.Interface Information*********************No IO constraint found====================================Detailed Report for Clock: DisplayDriverWrapper|button====================================Starting Points with Worst Slack********************************Starting ArrivalInstance Reference Type Pin Net Time SlackClock--------------------------------------------------------------------------------------------------------------------------------symbol_scan_cntr[1] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[1] 0.933 -0.398symbol_scan_cntr[2] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[2] 0.933 -0.398symbol_scan_cntr[3] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[3] 0.933 -0.339symbol_scan_cntr[4] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[4] 0.933 -0.339symbol_scan_cntr[5] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[5] 0.933 -0.280symbol_scan_cntr[6] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[6] 0.933 -0.280symbol_scan_cntr_fast[0] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr_fast[0] 0.753 -0.277symbol_scan_cntr[7] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[7] 0.798 0.570================================================================================================================================Ending Points with Worst Slack******************************Starting RequiredInstance Reference Type Pin Net Time SlackClock------------------------------------------------------------------------------------------------------------------------------symbol_scan_cntr[7] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[7] 2.044 -0.398symbol_scan_cntr[5] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[5] 2.044 -0.339symbol_scan_cntr[6] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[6] 2.044 -0.339symbol_scan_cntr[3] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[3] 2.044 -0.280symbol_scan_cntr[4] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[4] 2.044 -0.280symbol_scan_cntr[1] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[1] 2.044 -0.100symbol_scan_cntr[2] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[2] 2.044 -0.100symbol_scan_cntr[0] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[0] 2.044 0.570symbol_scan_cntr_fast[0] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[0] 2.044 0.570==============================================================================================================================Worst Path Information***********************Path information for path number 1:Requested Period: 2.255- Setup time: 0.211+ Clock delay at ending point: 0.000 (ideal)= Required time: 2.044- Propagation time: 2.442- Clock delay at starting point: 0.000 (ideal)= Slack (critical) : -0.398Number of logic level(s): 4Starting point: symbol_scan_cntr[1] / QEnding point: symbol_scan_cntr[7] / DThe start point is clocked by DisplayDriverWrapper|button [rising] on pin CKThe end point is clocked by DisplayDriverWrapper|button [rising] on pin CKInstance / Net Pin Pin Arrival No. ofName Type Name Dir Delay Time Fan Out(s)-------------------------------------------------------------------------------------------symbol_scan_cntr[1] FD1S3DX Q Out 0.933 0.933 -symbol_scan_cntr[1] Net - - - - 15symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -symbol_scan_cntr_cry[2] Net - - - - 1symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -symbol_scan_cntr_cry[4] Net - - - - 1symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -symbol_scan_cntr_cry[6] Net - - - - 1symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -symbol_scan_cntr_s[7] Net - - - - 1symbol_scan_cntr[7] FD1S3DX D In 0.000 2.442 -===========================================================================================Path information for path number 2:Requested Period: 2.255- Setup time: 0.211+ Clock delay at ending point: 0.000 (ideal)= Required time: 2.044- Propagation time: 2.442- Clock delay at starting point: 0.000 (ideal)= Slack (critical) : -0.398Number of logic level(s): 4Starting point: symbol_scan_cntr[2] / QEnding point: symbol_scan_cntr[7] / DThe start point is clocked by DisplayDriverWrapper|button [rising] on pin CKThe end point is clocked by DisplayDriverWrapper|button [rising] on pin CKInstance / Net Pin Pin Arrival No. ofName Type Name Dir Delay Time Fan Out(s)-------------------------------------------------------------------------------------------symbol_scan_cntr[2] FD1S3DX Q Out 0.933 0.933 -symbol_scan_cntr[2] Net - - - - 15symbol_scan_cntr_cry_0[1] CCU2C A1 In 0.000 0.933 -symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -symbol_scan_cntr_cry[2] Net - - - - 1symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -symbol_scan_cntr_cry[4] Net - - - - 1symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -symbol_scan_cntr_cry[6] Net - - - - 1symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -symbol_scan_cntr_s[7] Net - - - - 1symbol_scan_cntr[7] FD1S3DX D In 0.000 2.442 -===========================================================================================Path information for path number 3:Requested Period: 2.255- Setup time: 0.211+ Clock delay at ending point: 0.000 (ideal)= Required time: 2.044- Propagation time: 2.382- Clock delay at starting point: 0.000 (ideal)= Slack (non-critical) : -0.339Number of logic level(s): 3Starting point: symbol_scan_cntr[3] / QEnding point: symbol_scan_cntr[7] / DThe start point is clocked by DisplayDriverWrapper|button [rising] on pin CKThe end point is clocked by DisplayDriverWrapper|button [rising] on pin CKInstance / Net Pin Pin Arrival No. ofName Type Name Dir Delay Time Fan Out(s)-------------------------------------------------------------------------------------------symbol_scan_cntr[3] FD1S3DX Q Out 0.933 0.933 -symbol_scan_cntr[3] Net - - - - 15symbol_scan_cntr_cry_0[3] CCU2C A0 In 0.000 0.933 -symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.784 1.717 -symbol_scan_cntr_cry[4] Net - - - - 1symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.717 -symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.776 -symbol_scan_cntr_cry[6] Net - - - - 1symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.776 -symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.382 -symbol_scan_cntr_s[7] Net - - - - 1symbol_scan_cntr[7] FD1S3DX D In 0.000 2.382 -===========================================================================================Path information for path number 4:Requested Period: 2.255- Setup time: 0.211+ Clock delay at ending point: 0.000 (ideal)= Required time: 2.044- Propagation time: 2.382- Clock delay at starting point: 0.000 (ideal)= Slack (non-critical) : -0.339Number of logic level(s): 3Starting point: symbol_scan_cntr[4] / QEnding point: symbol_scan_cntr[7] / DThe start point is clocked by DisplayDriverWrapper|button [rising] on pin CKThe end point is clocked by DisplayDriverWrapper|button [rising] on pin CKInstance / Net Pin Pin Arrival No. ofName Type Name Dir Delay Time Fan Out(s)-------------------------------------------------------------------------------------------symbol_scan_cntr[4] FD1S3DX Q Out 0.933 0.933 -symbol_scan_cntr[4] Net - - - - 15symbol_scan_cntr_cry_0[3] CCU2C A1 In 0.000 0.933 -symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.784 1.717 -symbol_scan_cntr_cry[4] Net - - - - 1symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.717 -symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.776 -symbol_scan_cntr_cry[6] Net - - - - 1symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.776 -symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.382 -symbol_scan_cntr_s[7] Net - - - - 1symbol_scan_cntr[7] FD1S3DX D In 0.000 2.382 -===========================================================================================Path information for path number 5:Requested Period: 2.255- Setup time: 0.211+ Clock delay at ending point: 0.000 (ideal)= Required time: 2.044- Propagation time: 2.382- Clock delay at starting point: 0.000 (ideal)= Slack (non-critical) : -0.339Number of logic level(s): 3Starting point: symbol_scan_cntr[1] / QEnding point: symbol_scan_cntr[5] / DThe start point is clocked by DisplayDriverWrapper|button [rising] on pin CKThe end point is clocked by DisplayDriverWrapper|button [rising] on pin CKInstance / Net Pin Pin Arrival No. ofName Type Name Dir Delay Time Fan Out(s)-------------------------------------------------------------------------------------------symbol_scan_cntr[1] FD1S3DX Q Out 0.933 0.933 -symbol_scan_cntr[1] Net - - - - 15symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -symbol_scan_cntr_cry[2] Net - - - - 1symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -symbol_scan_cntr_cry[4] Net - - - - 1symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -symbol_scan_cntr_cry_0[5] CCU2C S0 Out 0.607 2.382 -symbol_scan_cntr_s[5] Net - - - - 1symbol_scan_cntr[5] FD1S3DX D In 0.000 2.382 -===========================================================================================##### END OF TIMING REPORT #####]Constraints that could not be appliedNoneFinished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)---------------------------------------Resource Usage ReportPart: lfe5um5g_45f-8Register bits: 9 of 43848 (0%)PIC Latch: 0I/O cells: 18Details:CCU2C: 5FD1S3DX: 9GSR: 1IB: 2INV: 1OB: 16PUR: 1ROM128X1A: 14VHI: 1VLO: 1Mapper successful!At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB)Process took 0h:00m:01s realtime, 0h:00m:01s cputime# Tue Jan 17 01:19:13 2017###########################################################]
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