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https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk
Subversion Repositories single-14-segment-display-driver-w-decoder
[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [synlog/] [DisplayDriverwDecoder_impl1_fpga_mapper.srr_Min] - Rev 5
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##### START OF TIMING REPORT #####[# Timing Report written on Fri Jan 13 00:54:42 2017#Top view: DisplayDriverWrapperRequested Frequency: 1220.4 MHzWire load mode: topPaths requested: 5Constraint File(s):@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.Performance Summary*******************Worst slack in design: 0.379Requested Estimated Requested Estimated Clock ClockStarting Clock Frequency Frequency Period Period Slack Type Group------------------------------------------------------------------------------------------------------------------------------------DisplayDriverWrapper|clk 1220.4 MHz 1037.3 MHz 0.819 0.964 -0.145 inferred Autoconstr_clkgroup_0====================================================================================================================================Clock Relationships*******************Clocks | rise to rise | fall to fall | rise to fall | fall to rise------------------------------------------------------------------------------------------------------------------------------------------Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack------------------------------------------------------------------------------------------------------------------------------------------DisplayDriverWrapper|clk DisplayDriverWrapper|clk | 0.000 0.379 | No paths - | No paths - | No paths -==========================================================================================================================================Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.Interface Information*********************No IO constraint found====================================Detailed Report for Clock: DisplayDriverWrapper|clk====================================Starting Points with Worst Slack********************************Starting ArrivalInstance Reference Type Pin Net Time SlackClock-------------------------------------------------------------------------------------------------------------DDwD_Top.ascii_reg[0] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[0] 0.527 0.379DDwD_Top.ascii_reg[1] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[1] 0.527 0.379DDwD_Top.ascii_reg[2] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[2] 0.527 0.379DDwD_Top.ascii_reg[3] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[3] 0.527 0.379DDwD_Top.ascii_reg[4] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[4] 0.527 0.379DDwD_Top.ascii_reg[5] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[5] 0.527 0.379DDwD_Top.ascii_reg[6] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[6] 0.527 0.379DDwD_Top.ascii_reg[7] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[7] 0.527 0.379=============================================================================================================Ending Points with Worst Slack******************************Starting RequiredInstance Reference Type Pin Net Time SlackClock--------------------------------------------------------------------------------------------------------------DDwD_Top.ascii_reg[0] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[0] 0.148 0.379DDwD_Top.ascii_reg[1] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[1] 0.148 0.379DDwD_Top.ascii_reg[2] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[2] 0.148 0.379DDwD_Top.ascii_reg[3] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[3] 0.148 0.379DDwD_Top.ascii_reg[4] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[4] 0.148 0.379DDwD_Top.ascii_reg[5] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[5] 0.148 0.379DDwD_Top.ascii_reg[6] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[6] 0.148 0.379DDwD_Top.ascii_reg[7] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[7] 0.148 0.379==============================================================================================================Worst Path Information***********************Path information for path number 1:Propagation time: 0.527+ Clock delay at starting point: 0.000 (ideal)- Requested Period: 0.000- Hold time: 0.148- Clock delay at ending point: 0.000 (ideal)= Slack (critical) : 0.379Number of logic level(s): 0Starting point: DDwD_Top.ascii_reg[0] / QEnding point: DDwD_Top.ascii_reg[0] / DThe start point is clocked by DisplayDriverWrapper|clk [rising] on pin CKThe end point is clocked by DisplayDriverWrapper|clk [rising] on pin CKInstance / Net Pin Pin Arrival No. ofName Type Name Dir Delay Time Fan Out(s)---------------------------------------------------------------------------------------DDwD_Top.ascii_reg[0] FD1S3IX Q Out 0.527 0.527 -ascii_reg[0] Net - - - - 1DDwD_Top.ascii_reg[0] FD1S3IX D In 0.000 0.527 -=======================================================================================##### END OF TIMING REPORT #####]Constraints that could not be appliedNone
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