Subversion Repositories single-14-segment-display-driver-w-decoder

Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1498R, Built Jul  5 2016 10:30:31
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.03L-1

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@A: MF827 |No constraint file specified.
@L: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1_scck.rpt 
Printing clock  summary report in "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1_scck.rpt" file 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)

ICG Latch Removal Summary:
Number of ICG latches removed:  0
Number of ICG latches not removed:      0
syn_allowed_resources : blockrams=108  set on top level netlist DisplayDriverWrapper

Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)



Clock Summary
*****************

Start                        Requested     Requested     Clock        Clock                     Clock
Clock                        Frequency     Period        Type         Group                     Load 
-----------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk     1.0 MHz       1000.000      inferred     Autoconstr_clkgroup_0     8    
=====================================================================================================

@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwdecoder_top.vhd":75:4:75:5|Found inferred clock DisplayDriverWrapper|clk which controls 8 sequential elements including DDwD_Top.ascii_reg[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

Finished Pre Mapping Phase.

Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)

None
None

Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sun Jan 08 00:49:34 2017

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