URL
https://opencores.org/ocsvn/single_port/single_port/trunk
Subversion Repositories single_port
[/] [single_port/] [trunk/] [doc/] [single_port.html] - Rev 15
Compare with Previous | Blame | View Log
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN">
<html>
<head>
<meta http-equiv="CONTENT-TYPE"
content="text/html; charset=iso-8859-1">
<title></title>
<meta name="GENERATOR" content="StarOffice/5.2 (Win32)">
<meta name="AUTHOR" content="Robert Paley">
<meta name="CREATED" content="20020728;14095738">
<meta name="CHANGEDBY" content="Robert Paley">
<meta name="CHANGED" content="20020728;15514460">
<style>
<!--
P.sdfootnote { margin-left: 0.2in; text-indent: -0.2in; margin-bottom: 0in; font-size: 10pt }
A.sdfootnoteanc { font-size: 57% }
-->
</style>
</head>
<body>
<p align="right"><font size="3"></font></p>
<h1 style="text-align: center;"><font size="4" style="font-size: 16pt;">Description
of single_port memory and test environment.</font></h1>
<h2>Abstract: </h2>
<p><span style="">A VHDL simulation model for an asynchronous static single
port memory is described. The memory is implemented as three different
architectures, a simple one and 2 ones which are optimized for efficient
use of simulator memory. Data and address buses are unconstrained, so
multiple instances with different address and data bus widths can be implemented
in one single design. </span>A testbench is also provided.<br>
</p>
<h2>Port Interface:</h2>
<table width="100%" border="1" cellpadding="5" cellspacing="4">
<col width="108"> <col width="118"> <col width="483"> <thead>
<tr valign="top">
<th width="108" bgcolor="#cccccc">
<p>Port Name</p>
</th>
<th width="118" bgcolor="#cccccc">
<p>Type</p>
</th>
<th width="483" bgcolor="#cccccc">
<p>Description</p>
</th>
</tr>
</thead> <tbody>
<tr valign="top">
<td width="108">
<p>rnwtQ</p>
</td>
<td width="118">
<p>Time</p>
</td>
<td width="483">
<p>Time delay until data or tristate appears on q data bus.</p>
</td>
</tr>
<tr valign="top">
<td width="108">
<p>d</p>
</td>
<td width="118"> STD_LOGIC_VECTOR<br>
</td>
<td width="483">
<p>Input data bus, unconstrained</p>
</td>
</tr>
<tr valign="top">
<td width="108">
<p>q</p>
</td>
<td width="118">
<p>STD_LOGIC_VECTOR<br>
</p>
</td>
<td width="483">
<p>Output data bus, unconstrained</p>
</td>
</tr>
<tr valign="top">
<td width="108">
<p>a</p>
</td>
<td width="118">
<p>STD_LOGIC_VECTOR<br>
</p>
</td>
<td width="483">
<p>Address bus, unconstrained</p>
</td>
</tr>
<tr valign="top">
<td width="108">
<p>nce</p>
</td>
<td width="118">
<p>STD_LOGIC</p>
</td>
<td width="483">
<p>not chip enable</p>
</td>
</tr>
<tr>
<td valign="top">nwe<br>
</td>
<td valign="top">STD_LOGIC<br>
</td>
<td valign="top">not write enable<br>
</td>
</tr>
<tr>
<td valign="top">noe<br>
</td>
<td valign="top">STD_LOGIC<br>
</td>
<td valign="top">not output enable<br>
</td>
</tr>
<tr valign="top">
<td width="108">
<p>dealloc_mem</p>
</td>
<td width="118">
<p>BOOLEAN</p>
</td>
<td width="483">
<p>When set to true, deallocate linked list memory.</p>
</td>
</tr>
</tbody>
</table>
<h2>Functional Description:</h2>
<p><span style="">All 3 architectures functionally behave like commercially
available asynchronous SRAMs if you connect d and q to the same bus. </span><span
style="">If a memory location is read which was not written to during the
current simulation, 'U's are loaded onto the memory bus.</span> </p>
<table cellpadding="2" cellspacing="2" border="1" width="100%">
<tbody>
<tr>
<th valign="top" bgcolor="#cccccc">nce<br>
</th>
<th valign="top" bgcolor="#cccccc">nwe<br>
</th>
<th valign="top" bgcolor="#cccccc">noe<br>
</th>
<th valign="top" bgcolor="#cccccc">d<br>
</th>
<th valign="top" bgcolor="#cccccc">q<br>
</th>
<th valign="top" bgcolor="#cccccc">Mode<br>
</th>
</tr>
<tr>
<td valign="top">1<br>
</td>
<td valign="top">don't care<br>
</td>
<td valign="top">don't care<br>
</td>
<td valign="top">don't care<br>
</td>
<td valign="top">high Z<br>
</td>
<td valign="top">deselected<br>
</td>
</tr>
<tr>
<td valign="top">0<br>
</td>
<td valign="top">1<br>
</td>
<td valign="top">1<br>
</td>
<td valign="top">don't care<br>
</td>
<td valign="top">high Z<br>
</td>
<td valign="top">output disabled<br>
</td>
</tr>
<tr>
<td valign="top">0<br>
</td>
<td valign="top">0<br>
</td>
<td valign="top">don't care<br>
</td>
<td valign="top">input data<br>
</td>
<td valign="top">high Z<br>
</td>
<td valign="top">write<br>
</td>
</tr>
<tr>
<td valign="top">0<br>
</td>
<td valign="top">1<br>
</td>
<td valign="top">0<br>
</td>
<td valign="top">don't care<br>
</td>
<td valign="top">RAM content<br>
</td>
<td valign="top">read<br>
</td>
</tr>
</tbody>
</table>
<h3>Architecture <span style="">ArrayMemNoFlag</span></h3>
<p><span style="">This architecture implements the memory core as an array
of STD_LOGIC_VECTOR. This is the simplest architecture. It is provided
for comparison with the models below but not recommended for use in your
design.</span></p>
<p><span style=""><o:p></o:p></span></p>
<h3><span style="">Architecture </span><span style="">ArrayMem</span></h3>
<p><span style="">This architecture i</span><span style="">mplements the
memory core as an array of BIT_VECTOR. This arrangement allows less workstation
memory to be used than the ArrayMemNoFlag architecture. Use this architecture
if most addresses in the simulated memory are written at least once.<br>
<o:p></o:p></span></p>
<h3><span style="">Architecture LinkedList</span></h3>
<h3><span style=""></span></h3>
<span style="">This architecture implements the memory core as a linked
list of arrays of BIT_VECTOR. Each array in the linked list is a page
of memory whose size is specified with the constant PAGEDEPTH in the package
linked_list_mem_pkg. This arrangement allows less workstation memory
to be used than either the ArrayMemNoFlag or ArrayMem architectures because
memory representing the array data is only allocated if the memory is
actually written to. To de-allocate the memory in the linked list, set
dealloc_mem to true. A short pulse is sufficient. Use this architecture
if a significant portion of your simulated memory (which need not be
contiguous) is never written to.</span>
<h2>Example Timing:</h2>
<p><span style="">Clearing both nce and nwe to to '0' immediately causes
a write operation. Changing the address while nce and nwe are asserted causes
a write to the new address, too (But don't do that with real RAMs because
you could destroy more memory locations while the address bus settles).
Every read (and tristate) operation is delayed rnwtQ ns. The below sample
timing diagram illustrates both a read and write operation.</span></p>
<p><img src="../images/timing.png" alt="Timing diagram" width="752"
height="515">
<br>
</p>
<h2>Testbench Description:</h2>
<p>The test bench is arranged as a client server architecture as specified
by Bergeron<a class="sdfootnoteanc" name="sdfootnote1anc"
href="#sdfootnote1sym"><sup>1</sup></a>. A diagram illustrating the testbench
is given below.</p>
<p><img src="../images/tbschematic.png" alt="Testbench schematic"
width="712" height="244">
<br clear="left">
Two tests are specified in tc_single_port component. The first test
writes data to two logical memory pages, and then reads them back verifying
the correct data. The test case writes an error message to the console
for every miscompare. The second case verifies that the single_port memory
model outputs unknowns to the q bus if a read occurs for an unwritten memory
location. Six configurations are specified in the test bench architecture
tb_single_port, running both tests for each single_port architecture. <br>
</p>
<h2>Usage:</h2>
<p>A Makefile is used to compile and run all of the tests in a Unix or like
environment, such as Cygwin. The compilation and simulation is targetted
to the SymphonyEDA tool available at <a
href="http://www.symphonyeda.com">www.symphonyeda.com</a>.</p>
<p>The source files and Makefile are located in {top}/VHDL<br>
<br>
To compile: make com</p>
<p>To simulate all of the tests: make sim<br>
</p>
<p>To clean the compiled library: make clean</p>
<p>The tests are labeled :</p>
<ul>
<li>ll_error</li>
<li>ll_main</li>
<li>mem_main<br>
</li>
<li>mem_error<br>
</li>
<li>memnoflag_main<br>
</li>
<li>memnoflag_error<br>
</li>
</ul>
<p>To simulate any of these tests, type make {testname}</p>
<p>Please contact Robert Paley at <a href="mailto:rpaley_yid@yahoo.com">rpaley_yid@opencores.org</a>
or Michael Geng at <a href="mailto:vhdl@michaelgeng.de">vhdl@michaelgeng.de</a>
if you have any questions or comments. </p>
<div id="sdfootnote1">
<p class="sdfootnote" style="margin-bottom: 0.2in;"><a
class="sdfootnotesym" name="sdfootnote1sym" href="#sdfootnote1anc">1</a>Writing
Testbenches , Functional Verification of HDL Testbenches. Chapter 6 –
ISBN 0-7923-7766-4<br>
</p>
</div>
<br>
<br>
<br>
</body>
</html>