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[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [nexys2/] [ip/] [iceskate/] [sim/] [testbenches/] [verilog/] [tb.ext] - Rev 135
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reg [3:0] btn_reg;
reg [7:0] sw_reg;
assign A_CLK = clk;
assign CTS = reset;
assign SW = sw_reg;
assign BTN = btn_reg;
assign STOP = 1'b0;
assign BAD = 1'b0;