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[/] [socgen/] [trunk/] [Projects/] [lattice.com/] [fpgas/] [ip/] [iceskate/] [sim/] [testbenches/] [xml/] [fpgas_iceskate_dut.design.xml] - Rev 135
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<?xml version="1.0" encoding="UTF-8"?>
<!--
//
// //
// ./tools/verilog/gen_tb -vendor opencores.org -library fpgas -component iceskate -version default //
// //
-->
<ipxact:design
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
<ipxact:vendor>lattice.com</ipxact:vendor>
<ipxact:library>fpgas</ipxact:library>
<ipxact:name>iceskate</ipxact:name>
<ipxact:version>dut.design</ipxact:version>
<ipxact:adHocConnections>
<ipxact:adHocConnection>
<ipxact:name>CLK</ipxact:name>
<ipxact:externalPortReference portRef="CLK" />
<ipxact:internalPortReference componentRef="dut" portRef="CLK" />
</ipxact:adHocConnection>
</ipxact:adHocConnections>
<ipxact:componentInstances>
<ipxact:componentInstance>
<ipxact:instanceName>dut</ipxact:instanceName>
<ipxact:componentRef vendor="lattice.com" library="fpgas" name="iceskate" version="default" />
<ipxact:configurableElementValues>
</ipxact:configurableElementValues>
</ipxact:componentInstance>
</ipxact:componentInstances>
</ipxact:design>