OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [doc/] [sym/] [cpu_def.sym] - Rev 135

Compare with Previous | Blame | View Log

v 20100214 1
B 300 0  3400 1900 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 2050   5 10 1 1 0 0 1 1
device=cpu_def
T 400 2250 5 10 1 1 0 0 1 1
refdes=U?
T 400 2400    0 10 0 1 0 0 1 1
vendor=opencores.org
T 400 2400    0 10 0 1 0 0 1 1
library=Mos6502
T 400 2400    0 10 0 1 0 0 1 1
component=cpu
T 400 2400    0 10 0 1 0 0 1 1
version=def
P 300 200 0 200 10 1 1 
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=vec_int[7:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 10 1 1 
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=rdata[15:0]
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 10 1 1 
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=pg0_data[7:0]
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 300 800 0 800 4 0 1  
{
T 400 800 5 10 1 1 0 1 1 1 
pinnumber=reset
T 400 800 5 10 0 1 0 1 1 1 
pinseq=4
}
P 300 1000 0 1000 4 0 1  
{
T 400 1000 5 10 1 1 0 1 1 1 
pinnumber=nmi
T 400 1000 5 10 0 1 0 1 1 1 
pinseq=5
}
P 300 1200 0 1200 4 0 1  
{
T 400 1200 5 10 1 1 0 1 1 1 
pinnumber=enable
T 400 1200 5 10 0 1 0 1 1 1 
pinseq=6
}
P 300 1400 0 1400 4 0 1  
{
T 400 1400 5 10 1 1 0 1 1 1 
pinnumber=clk
T 400 1400 5 10 0 1 0 1 1 1 
pinseq=7
}
P 3700 200 4000 200 10 1 1
{
T 3600 200 5  10 1 1 0 7 1 1 
pinnumber=wdata[7:0]
T 3600 200 5  10 0 1 0 7 1 1 
pinseq=8
}
P 3700 400 4000 400 10 1 1
{
T 3600 400 5  10 1 1 0 7 1 1 
pinnumber=pg0_add[7:0]
T 3600 400 5  10 0 1 0 7 1 1 
pinseq=9
}
P 3700 600 4000 600 10 1 1
{
T 3600 600 5  10 1 1 0 7 1 1 
pinnumber=alu_status[7:0]
T 3600 600 5  10 0 1 0 7 1 1 
pinseq=10
}
P 3700 800 4000 800 10 1 1
{
T 3600 800 5  10 1 1 0 7 1 1 
pinnumber=addr[CPU_ADD-1:0]
T 3600 800 5  10 0 1 0 7 1 1 
pinseq=11
}
P 3700 1000 4000 1000 4 0 1
{
T 3600 1000 5  10 1 1 0 7 1 1
pinnumber=wr
T 3700 1000 5  10 0 1 0 7 1 1
pinseq=12
}
P 3700 1200 4000 1200 4 0 1
{
T 3600 1200 5  10 1 1 0 7 1 1
pinnumber=rd
T 3700 1200 5  10 0 1 0 7 1 1
pinseq=13
}
P 3700 1400 4000 1400 4 0 1
{
T 3600 1400 5  10 1 1 0 7 1 1
pinnumber=pg0_wr
T 3700 1400 5  10 0 1 0 7 1 1
pinseq=14
}
P 3700 1600 4000 1600 4 0 1
{
T 3600 1600 5  10 1 1 0 7 1 1
pinnumber=pg0_rd
T 3700 1600 5  10 0 1 0 7 1 1
pinseq=15
}

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.