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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [doc/] [sch/] [T6502_def.sch] - Rev 135

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v 20100214 1
C 2600 300 1 0 0 in_port_vector.sym   
{
T 2600 300 5 10 1 1 0 6 1 1
refdes=wb_jsp_dat_i[7:0]
}
C 2600 700 1 0 0 in_port_vector.sym   
{
T 2600 700 5 10 1 1 0 6 1 1
refdes=gpio_1_in[7:0]
}
C 2600 1100 1 0 0 in_port_vector.sym   
{
T 2600 1100 5 10 1 1 0 6 1 1
refdes=gpio_0_in[7:0]
}
C 2600 1500 1 0 0 in_port_vector.sym   
{
T 2600 1500 5 10 1 1 0 6 1 1
refdes=ext_rdata[15:0]
}
C 2600 1900 1 0 0 in_port_vector.sym   
{
T 2600 1900 5 10 1 1 0 6 1 1
refdes=ext_irq_in[3:0]
}
C 2600 2300 1 0 0 in_port.sym  
{
T 2600 2300 5 10 1 1 0 6 1 1 
refdes=wb_jsp_stb_i
}
C 2600 2700 1 0 0 in_port.sym  
{
T 2600 2700 5 10 1 1 0 6 1 1 
refdes=uart_rxd_pad_in
}
C 2600 3100 1 0 0 in_port.sym  
{
T 2600 3100 5 10 1 1 0 6 1 1 
refdes=reset
}
C 2600 3500 1 0 0 in_port.sym  
{
T 2600 3500 5 10 1 1 0 6 1 1 
refdes=ps2_data_pad_in
}
C 2600 3900 1 0 0 in_port.sym  
{
T 2600 3900 5 10 1 1 0 6 1 1 
refdes=ps2_clk_pad_in
}
C 2600 4300 1 0 0 in_port.sym  
{
T 2600 4300 5 10 1 1 0 6 1 1 
refdes=jtag_update_dr_clk
}
C 2600 4700 1 0 0 in_port.sym  
{
T 2600 4700 5 10 1 1 0 6 1 1 
refdes=jtag_test_logic_reset
}
C 2600 5100 1 0 0 in_port.sym  
{
T 2600 5100 5 10 1 1 0 6 1 1 
refdes=jtag_tdi
}
C 2600 5500 1 0 0 in_port.sym  
{
T 2600 5500 5 10 1 1 0 6 1 1 
refdes=jtag_shiftcapture_dr_clk
}
C 2600 5900 1 0 0 in_port.sym  
{
T 2600 5900 5 10 1 1 0 6 1 1 
refdes=jtag_shift_dr
}
C 2600 6300 1 0 0 in_port.sym  
{
T 2600 6300 5 10 1 1 0 6 1 1 
refdes=jtag_select
}
C 2600 6700 1 0 0 in_port.sym  
{
T 2600 6700 5 10 1 1 0 6 1 1 
refdes=jtag_capture_dr
}
C 2600 7100 1 0 0 in_port.sym  
{
T 2600 7100 5 10 1 1 0 6 1 1 
refdes=ext_wait
}
C 2600 7500 1 0 0 in_port.sym  
{
T 2600 7500 5 10 1 1 0 6 1 1 
refdes=cts_pad_in
}
C 2600 7900 1 0 0 in_port.sym  
{
T 2600 7900 5 10 1 1 0 6 1 1 
refdes=clk
}
C 6100 300  1 0  0 out_port_vector.sym
{
T 7100 300 5  10 1 1 0 0 1 1 
refdes=vga_red_pad_out[2:0]
}
C 6100 700  1 0  0 out_port_vector.sym
{
T 7100 700 5  10 1 1 0 0 1 1 
refdes=vga_green_pad_out[2:0]
}
C 6100 1100  1 0  0 out_port_vector.sym
{
T 7100 1100 5  10 1 1 0 0 1 1 
refdes=vga_blue_pad_out[1:0]
}
C 6100 1500  1 0  0 out_port_vector.sym
{
T 7100 1500 5  10 1 1 0 0 1 1 
refdes=jsp_data_out[7:0]
}
C 6100 1900  1 0  0 out_port_vector.sym
{
T 7100 1900 5  10 1 1 0 0 1 1 
refdes=gpio_1_out[7:0]
}
C 6100 2300  1 0  0 out_port_vector.sym
{
T 7100 2300 5  10 1 1 0 0 1 1 
refdes=gpio_1_oe[7:0]
}
C 6100 2700  1 0  0 out_port_vector.sym
{
T 7100 2700 5  10 1 1 0 0 1 1 
refdes=gpio_0_out[7:0]
}
C 6100 3100  1 0  0 out_port_vector.sym
{
T 7100 3100 5  10 1 1 0 0 1 1 
refdes=gpio_0_oe[7:0]
}
C 6100 3500  1 0  0 out_port_vector.sym
{
T 7100 3500 5  10 1 1 0 0 1 1 
refdes=ext_wdata[15:0]
}
C 6100 3900  1 0  0 out_port_vector.sym
{
T 7100 3900 5  10 1 1 0 0 1 1 
refdes=ext_cs[1:0]
}
C 6100 4300  1 0  0 out_port_vector.sym
{
T 7100 4300 5  10 1 1 0 0 1 1 
refdes=ext_addr[23:1]
}
C 6100 4700  1 0  0 out_port_vector.sym
{
T 7100 4700 5  10 1 1 0 0 1 1 
refdes=alu_status[7:0]
}
C 6100 5100  1 0 0 out_port.sym
{
T 7100 5100 5  10 1 1 0 0 1 1
refdes=vga_vsync_n_pad_out
}
C 6100 5500  1 0 0 out_port.sym
{
T 7100 5500 5  10 1 1 0 0 1 1
refdes=vga_hsync_n_pad_out
}
C 6100 5900  1 0 0 out_port.sym
{
T 7100 5900 5  10 1 1 0 0 1 1
refdes=uart_txd_pad_out
}
C 6100 6300  1 0 0 out_port.sym
{
T 7100 6300 5  10 1 1 0 0 1 1
refdes=rts_pad_out
}
C 6100 6700  1 0 0 out_port.sym
{
T 7100 6700 5  10 1 1 0 0 1 1
refdes=ps2_data_pad_oe
}
C 6100 7100  1 0 0 out_port.sym
{
T 7100 7100 5  10 1 1 0 0 1 1
refdes=ps2_clk_pad_oe
}
C 6100 7500  1 0 0 out_port.sym
{
T 7100 7500 5  10 1 1 0 0 1 1
refdes=jtag_tdo
}
C 6100 7900  1 0 0 out_port.sym
{
T 7100 7900 5  10 1 1 0 0 1 1
refdes=ext_wr
}
C 6100 8300  1 0 0 out_port.sym
{
T 7100 8300 5  10 1 1 0 0 1 1
refdes=ext_ub
}
C 6100 8700  1 0 0 out_port.sym
{
T 7100 8700 5  10 1 1 0 0 1 1
refdes=ext_stb
}
C 6100 9100  1 0 0 out_port.sym
{
T 7100 9100 5  10 1 1 0 0 1 1
refdes=ext_rd
}
C 6100 9500  1 0 0 out_port.sym
{
T 7100 9500 5  10 1 1 0 0 1 1
refdes=ext_lb
}
C 6100 9900  1 0 0 out_port.sym
{
T 7100 9900 5  10 1 1 0 0 1 1
refdes=biu_wr_strobe
}

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