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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [sim/] [testbenches/] [verilog/] [tb.ext_m] - Rev 131

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assign ext_irq_in = 4'h0;

pullup mdb_00(MEMDB[00]);
pullup mdb_01(MEMDB[01]);
pullup mdb_02(MEMDB[02]);
pullup mdb_03(MEMDB[03]);
pullup mdb_04(MEMDB[04]);
pullup mdb_05(MEMDB[05]);
pullup mdb_06(MEMDB[06]);
pullup mdb_07(MEMDB[07]);
pullup mdb_08(MEMDB[08]);
pullup mdb_09(MEMDB[09]);
pullup mdb_10(MEMDB[10]);
pullup mdb_11(MEMDB[11]);
pullup mdb_12(MEMDB[12]);
pullup mdb_13(MEMDB[13]);
pullup mdb_14(MEMDB[14]);
pullup mdb_15(MEMDB[15]);

pullup pu_ramwait ( ramwait_in );

mt45w8mw12_def
psram (
    .clk    ( ramclk_out    ), 
    .adv_n  ( ramadv_n_out  ),
    .cre    ( ramcre_out    ), 
    .o_wait ( ramwait_in    ),
    .ce_n   ( ramcs_n_out   ),
    .oe_n   ( memoe_n_out   ),
    .we_n   ( memwr_n_out   ),
    .lb_n   ( ramlb_n_out   ),
    .ub_n   ( ramub_n_out   ),
    .addr   ( memadr_out    ),
    .dq     ( MEMDB         ) 
); 


assign STOP = 1'b0;
assign BAD = 1'b0;

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