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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [sim/] [testbenches/] [verilog/] [tb.int_m] - Rev 131
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assign ext_irq_in = 4'h0;assign cts_pad_in = 1'b0;assign ext_wait = 1'b0;assign ps2_clk_pad_in = 1'b0;assign ps2_data_pad_in = 1'b0;assign uart_rxd_pad_in = 1'b0;assign ext_rdata = 16'b0;assign gpio_0_in = 8'b0;assign gpio_1_in = 8'b0;