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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [core/] [rtl/] [verilog/] [defines] - Rev 131
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`define RESET 4'b0000`define HALT 4'b0001`define AXE_1 4'b0011`define FETCH_OP 4'b0100`define EXECUTE 4'b0101`define EXE_1 4'b0110`define AXE_2 4'b0111`define IDX_1 4'b1000`define IDX_2 4'b1001`define IDX_3 4'b1010`define IDY_1 4'b1011`define IDY_2 4'b1100`define IDY_3 4'b1101`define INT_1 4'b1110`define INT_2 4'b1111// alu_mode`define alu_mode_add 3'b000`define alu_mode_and 3'b001`define alu_mode_orr 3'b010`define alu_mode_eor 3'b011`define alu_mode_sfl 3'b100`define alu_mode_sfr 3'b101`define alu_mode_afl 3'b110`define alu_mode_afr 3'b111// alu_op_a_sel`define alu_op_a_00 3'b000`define alu_op_a_acc 3'b001`define alu_op_a_x 3'b010`define alu_op_a_y 3'b011`define alu_op_a_ff 3'b100`define alu_op_a_psr 3'b101// alu_op_b_sel`define alu_op_b_00 2'b00`define alu_op_b_imm 2'b01`define alu_op_b_stk 2'b10`define alu_op_b_opnd 2'b11// alu_op_b_inv// alu_op_c_sel`define alu_op_c_00 2'b00`define alu_op_c_01 2'b01`define alu_op_c_cin 2'b10`define alu_op_c_xx 2'b11// alu_status_update`define alu_status_update_none 5'b00000`define alu_status_update_nz 5'b00001`define alu_status_update_nzc 5'b00011`define alu_status_update_nzcv 5'b00111`define alu_status_update_wr 5'b01000`define alu_status_update_z67 5'b10000`define alu_status_update_res 5'b11000// dest`define dest_none 3'b000`define dest_alu_a 3'b001`define dest_alu_x 3'b010`define dest_alu_y 3'b011`define dest_mem 3'b100// ctrl`define ctrl_none 3'b000`define ctrl_jsr 3'b001`define ctrl_jmp 3'b010`define ctrl_jmp_ind 3'b011`define ctrl_brk 3'b100`define ctrl_rti 3'b101`define ctrl_rts 3'b110`define ctrl_branch 3'b111// cmd`define cmd_none 2'b00`define cmd_run 2'b01`define cmd_load_add 2'b10`define cmd_load_vec 2'b11// ins_type`define ins_type_none 2'b00`define ins_type_read 2'b01`define ins_type_write 2'b10`define ins_type_rmw 2'b11// idx_sel`define idx_sel_00 2'b00`define idx_sel_x 2'b01`define idx_sel_y 2'b10//////////////////////////////////////////////////////////////////////////////// //////// Processor Status Register //////// //////////////////////////////////////////////////////////////////////////////////// //////// C - Carry Flag //////// Z - Zero Flag //////// I - Interrupt Disable //////// D - Decimal Mode //////// B - Break Command //////// 1 - Constant One //////// V - oVerflow Flag //////// N - Negative Flag //////// //////////////////////////////////////////////////////////////////////////////////// //////// ------------------------------------------------- //////// | N | V | 1 | B | D | I | Z | C | //////// ------------------------------------------------- //////// ////////////////////////////////////////////////////////////////////////////////`define C 3'b000`define Z 3'b001`define I 3'b010`define D 3'b011`define B 3'b100`define V 3'b110`define N 3'b111`define ADC_IMM 8'h69`define ADC_ZPG 8'h65`define ADC_ZPX 8'h75`define ADC_ABS 8'h6D`define ADC_ABX 8'h7D`define ADC_ABY 8'h79`define ADC_IDX 8'h61`define ADC_IDY 8'h71`define AND_IMM 8'h29`define AND_ZPG 8'h25`define AND_ZPX 8'h35`define AND_ABS 8'h2D`define AND_ABX 8'h3D`define AND_ABY 8'h39`define AND_IDX 8'h21`define AND_IDY 8'h31`define ASL_ACC 8'h0A`define ASL_ZPG 8'h06`define ASL_ZPX 8'h16`define ASL_ABS 8'h0E`define ASL_ABX 8'h1E`define BCC_REL 8'h90`define BCS_REL 8'hB0`define BEQ_REL 8'hF0`define BMI_REL 8'h30`define BNE_REL 8'hD0`define BPL_REL 8'h10`define BVC_REL 8'h50`define BVS_REL 8'h70`define BIT_ZPG 8'h24`define BIT_ABS 8'h2C`define BRK_IMP 8'h00`define CLC_IMP 8'h18`define CLD_IMP 8'hD8`define CLI_IMP 8'h58`define CLV_IMP 8'hB8`define CMP_IMM 8'hC9`define CMP_ZPG 8'hC5`define CMP_ZPX 8'hD5`define CMP_ABS 8'hCD`define CMP_ABX 8'hDD`define CMP_ABY 8'hD9`define CMP_IDX 8'hC1`define CMP_IDY 8'hD1`define CPX_IMM 8'hE0`define CPX_ZPG 8'hE4`define CPX_ABS 8'hEC`define CPY_IMM 8'hC0`define CPY_ZPG 8'hC4`define CPY_ABS 8'hCC`define DEC_ZPG 8'hC6`define DEC_ZPX 8'hD6`define DEC_ABS 8'hCE`define DEC_ABX 8'hDE`define DEX_IMP 8'hCA`define DEY_IMP 8'h88`define EOR_IMM 8'h49`define EOR_ZPG 8'h45`define EOR_ZPX 8'h55`define EOR_ABS 8'h4D`define EOR_ABX 8'h5D`define EOR_ABY 8'h59`define EOR_IDX 8'h41`define EOR_IDY 8'h51`define INC_ZPG 8'hE6`define INC_ZPX 8'hF6`define INC_ABS 8'hEE`define INC_ABX 8'hFE`define INX_IMP 8'hE8`define INY_IMP 8'hC8`define JMP_ABS 8'h4C`define JMP_IND 8'h6C`define JSR_ABS 8'h20`define LDA_IMM 8'hA9`define LDA_ZPG 8'hA5`define LDA_ZPX 8'hB5`define LDA_ABS 8'hAD`define LDA_ABX 8'hBD`define LDA_ABY 8'hB9`define LDA_IDX 8'hA1`define LDA_IDY 8'hB1`define LDX_IMM 8'hA2`define LDX_ZPG 8'hA6`define LDX_ZPY 8'hB6`define LDX_ABS 8'hAE`define LDX_ABY 8'hBE`define LDY_IMM 8'hA0`define LDY_ZPG 8'hA4`define LDY_ZPX 8'hB4`define LDY_ABS 8'hAC`define LDY_ABX 8'hBC`define LSR_ACC 8'h4A`define LSR_ZPG 8'h46`define LSR_ZPX 8'h56`define LSR_ABS 8'h4E`define LSR_ABX 8'h5E`define NOP_IMP 8'hEA`define ORA_IMM 8'h09`define ORA_ZPG 8'h05`define ORA_ZPX 8'h15`define ORA_ABS 8'h0D`define ORA_ABX 8'h1D`define ORA_ABY 8'h19`define ORA_IDX 8'h01`define ORA_IDY 8'h11`define PHA_IMP 8'h48`define PHP_IMP 8'h08`define PLA_IMP 8'h68`define PLP_IMP 8'h28`define ROL_ACC 8'h2A`define ROL_ZPG 8'h26`define ROL_ZPX 8'h36`define ROL_ABS 8'h2E`define ROL_ABX 8'h3E`define ROR_ACC 8'h6A`define ROR_ZPG 8'h66`define ROR_ZPX 8'h76`define ROR_ABS 8'h6E`define ROR_ABX 8'h7E`define RTI_IMP 8'h40`define RTS_IMP 8'h60`define SBC_IMM 8'hE9`define SBC_ZPG 8'hE5`define SBC_ZPX 8'hF5`define SBC_ABS 8'hED`define SBC_ABX 8'hFD`define SBC_ABY 8'hF9`define SBC_IDX 8'hE1`define SBC_IDY 8'hF1`define SEC_IMP 8'h38`define SED_IMP 8'hF8`define SEI_IMP 8'h78`define STA_ZPG 8'h85`define STA_ZPX 8'h95`define STA_ABS 8'h8D`define STA_ABX 8'h9D`define STA_ABY 8'h99`define STA_IDX 8'h81`define STA_IDY 8'h91`define STX_ZPG 8'h86`define STX_ZPY 8'h96`define STX_ABS 8'h8E`define STY_ZPG 8'h84`define STY_ZPX 8'h94`define STY_ABS 8'h8C`define TAX_IMP 8'hAA`define TAY_IMP 8'hA8`define TXA_IMP 8'h8A`define TYA_IMP 8'h98