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//=============================================================================
//    Rtl Glue Logic
//============================================================================= 
        
   assign cpu_pg0_data             =   pg0_add[0]?pg0_data[15:8]:pg0_data[7:0];
   assign prog_rom_wr              =   we_pin && CSP;
   assign prog_rom_wdata           =  {write_data,write_data};
   assign core_ram_l_cs            =   CSD && (!addr_in[0]);
   assign core_ram_h_cs            =   CSD && ( addr_in[0]);
   assign pg00_ram_rd              =   pg0_rd||(CS0 && rd_pin);
   assign pg00_ram_l_wr            =  (pg0_wr||(CS0 && we_pin)) && (!pg0_add[0]);
   assign pg00_ram_h_wr            =  (pg0_wr||(CS0 && we_pin)) && ( pg0_add[0]);
   assign io_module_pic_irq_in     =  {ext_irq_in[2:0],ps2_data_avail,tx_irq,rx_irq,timer_irq};
   assign io_module_vic_irq_in     =  {ext_irq_in[2:0],ps2_data_avail,tx_irq,rx_irq,timer_irq};

//=============================================================================
//    
//=============================================================================