OpenCores
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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [core/] [rtl/] [xml/] [core_def.xml] - Rev 131

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<?xml version="1.0" encoding="UTF-8"?>
<!--
//                                                                        //
// Author : John Eaton  Ouabache Designworks                              //
//                                                                        //
//   Copyright (C) 2010 Authors and OPENCORES.ORG                         //
//                                                                        //
//   This source file may be used and distributed without                 //
//   restriction provided that this copyright statement is not            //
//   removed from the file and that any derivative work contains          //
//   the original copyright notice and the associated disclaimer.         //
//                                                                        //
//   This source file is free software; you can redistribute it           //
//   and/or modify it under the terms of the GNU Lesser General           //
//   Public License as published by the Free Software Foundation;         //
//   either version 2.1 of the License, or (at your option) any           //
//   later version.                                                       //
//                                                                        //
//   This source is distributed in the hope that it will be               //
//   useful, but WITHOUT ANY WARRANTY; without even the implied           //
//   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR              //
//   PURPOSE. See the GNU Lesser General Public License for more          //
//   details.                                                             //
//                                                                        //
//   You should have received a copy of the GNU Lesser General            //
//   Public License along with this source; if not, download it           //
//   from http://www.opencores.org/lgpl.shtml                             //
//                                                                        //
-->
<spirit:component 
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">

<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>Mos6502</spirit:library>
<spirit:name>core</spirit:name>
<spirit:version>def</spirit:version>  <spirit:configuration>default</spirit:configuration>  

<spirit:busInterfaces>

 <spirit:busInterface><spirit:name>slave_clk</spirit:name>
  <spirit:busType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="clock" spirit:version="def"/>
  <spirit:abstractionType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="clock" spirit:version="rtl"/>
  <spirit:slave/>
    <spirit:portMaps>
      <spirit:portMap>
        <spirit:logicalPort><spirit:name>clk</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>clk</spirit:name></spirit:physicalPort>
      </spirit:portMap>
    </spirit:portMaps>
 </spirit:busInterface>


 <spirit:busInterface><spirit:name>slave_reset</spirit:name>
  <spirit:busType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="reset" spirit:version="def"/>
  <spirit:abstractionType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="reset" spirit:version="rtl"/>
  <spirit:slave/>
    <spirit:portMaps>
      <spirit:portMap>
        <spirit:logicalPort><spirit:name>reset</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>reset</spirit:name></spirit:physicalPort>
      </spirit:portMap>
    </spirit:portMaps>
 </spirit:busInterface>





 <spirit:busInterface><spirit:name>cpu</spirit:name>
  <spirit:busType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="micro_bus" spirit:version="def"/>
  <spirit:abstractionType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="micro_bus" spirit:version="rtl"/>
  <spirit:master/>
    <spirit:portMaps>
      <spirit:portMap>
        <spirit:logicalPort><spirit:name>addr</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>addr</spirit:name>
        <spirit:wire><spirit:vector><spirit:left>15</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>
      <spirit:portMap>
        <spirit:logicalPort><spirit:name>rdata</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>rdata</spirit:name>
        <spirit:wire><spirit:vector><spirit:left>15</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>
      <spirit:portMap>
        <spirit:logicalPort><spirit:name>wdata</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>wdata</spirit:name>
        <spirit:wire><spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
        </spirit:physicalPort>
      </spirit:portMap>
      <spirit:portMap>
        <spirit:logicalPort><spirit:name>rd</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>rd</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>
      <spirit:portMap>
        <spirit:logicalPort><spirit:name>wr</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>wr</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>
    </spirit:portMaps>
 </spirit:busInterface>



</spirit:busInterfaces>

<spirit:componentGenerators>






<spirit:componentGenerator>
  <spirit:name>gen_verilog_sim</spirit:name>
  <spirit:phase>104.0</spirit:phase>
  <spirit:apiType>none</spirit:apiType>
  <spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
  <spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe>  
  <spirit:parameters>
    <spirit:parameter> 
      <spirit:name>destination</spirit:name>
      <spirit:value>top.out.sim</spirit:value>
    </spirit:parameter>
    <spirit:parameter> 
      <spirit:name>dest_dir</spirit:name>
      <spirit:value>../verilog</spirit:value>
    </spirit:parameter>
  </spirit:parameters>
</spirit:componentGenerator>

<spirit:componentGenerator>
  <spirit:name>gen_verilog_syn</spirit:name>
  <spirit:phase>104.0</spirit:phase>
  <spirit:apiType>none</spirit:apiType>
  <spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions>
  <spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe>  
  <spirit:parameters>
    <spirit:parameter> 
      <spirit:name>destination</spirit:name>
      <spirit:value>top.out.syn</spirit:value>
    </spirit:parameter>
    <spirit:parameter> 
      <spirit:name>dest_dir</spirit:name>
      <spirit:value>../verilog</spirit:value>
    </spirit:parameter>
  </spirit:parameters>
</spirit:componentGenerator>




</spirit:componentGenerators>





  <spirit:fileSets>


    <spirit:fileSet>
      <spirit:name>fs-sim</spirit:name>

      <spirit:file>
        <spirit:logicalName></spirit:logicalName>
        <spirit:name>../verilog/copyright.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
      </spirit:file>

      <spirit:file>
        <spirit:logicalName></spirit:logicalName>
        <spirit:name>../verilog/sim/top.out.sim</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
      </spirit:file>



      <spirit:file>
        <spirit:logicalName></spirit:logicalName>
        <spirit:name>../verilog/defines</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
      </spirit:file>


      <spirit:file>
        <spirit:logicalName>alu</spirit:logicalName>
        <spirit:name>../verilog/alu</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
      </spirit:file>

      <spirit:file>
        <spirit:logicalName>alu_logic</spirit:logicalName>
        <spirit:name>../verilog/alu_logic</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
      </spirit:file>


      <spirit:file>
        <spirit:logicalName>control</spirit:logicalName>
        <spirit:name>../verilog/control</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
      </spirit:file>


      <spirit:file>
        <spirit:logicalName>inst_decode</spirit:logicalName>
        <spirit:name>../verilog/inst_decode</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
      </spirit:file>

      <spirit:file>
        <spirit:logicalName>sequencer</spirit:logicalName>
        <spirit:name>../verilog/sequencer</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
      </spirit:file>



      <spirit:file>
        <spirit:logicalName>state_fsm</spirit:logicalName>
        <spirit:name>../verilog/state_fsm</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
      </spirit:file>


      <spirit:file>
        <spirit:logicalName></spirit:logicalName>
        <spirit:name>../verilog/top.sim</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType>
      </spirit:file>

      <spirit:file>
        <spirit:logicalName></spirit:logicalName>
        <spirit:name>../verilog/top.body</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType>
      </spirit:file>




    </spirit:fileSet>



    <spirit:fileSet>
      <spirit:name>fs-syn</spirit:name>

      <spirit:file>
        <spirit:logicalName></spirit:logicalName>
        <spirit:name>../verilog/copyright.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
      </spirit:file>


      <spirit:file>
        <spirit:logicalName></spirit:logicalName>
        <spirit:name>../verilog/syn/top.out.syn</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
      </spirit:file>

      <spirit:file>
        <spirit:logicalName></spirit:logicalName>
        <spirit:name>../verilog/defines</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
      </spirit:file>


      <spirit:file>
        <spirit:logicalName>alu</spirit:logicalName>
        <spirit:name>../verilog/alu</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
      </spirit:file>

      <spirit:file>
        <spirit:logicalName>alu_logic</spirit:logicalName>
        <spirit:name>../verilog/alu_logic</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
      </spirit:file>


      <spirit:file>
        <spirit:logicalName>control</spirit:logicalName>
        <spirit:name>../verilog/control</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
      </spirit:file>


      <spirit:file>
        <spirit:logicalName>inst_decode</spirit:logicalName>
        <spirit:name>../verilog/inst_decode</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
      </spirit:file>

      <spirit:file>
        <spirit:logicalName>sequencer</spirit:logicalName>
        <spirit:name>../verilog/sequencer</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
      </spirit:file>



      <spirit:file>
        <spirit:logicalName>state_fsm</spirit:logicalName>
        <spirit:name>../verilog/state_fsm</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
      </spirit:file>



      <spirit:file>
        <spirit:logicalName></spirit:logicalName>
        <spirit:name>../verilog/top.body</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType>
      </spirit:file>


    </spirit:fileSet>





  </spirit:fileSets>



   
<spirit:model>    
       <spirit:views>

       <spirit:view>
       <spirit:name>Hierarchical</spirit:name>
       <spirit:hierarchyRef spirit:vendor="opencores.org" 
                            spirit:library="Mos6502" 
                            spirit:name="core" 
                            spirit:version="def.design"/>
       </spirit:view>


              <spirit:view>
              <spirit:name>verilog</spirit:name>              
              <spirit:vendorExtensions>
              <spirit:componentRef spirit:vendor="opencores.org" 
                                   spirit:library="Testbench" 
                                   spirit:name="toolflow" 
                                   spirit:version="verilog"/> 
              </spirit:vendorExtensions>
              </spirit:view>





       <spirit:view>
       <spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier>
       <spirit:language>Verilog</spirit:language>
       <spirit:fileSetRef><spirit:localName>fs-sim</spirit:localName></spirit:fileSetRef>
       </spirit:view>

       <spirit:view>
       <spirit:name>syn</spirit:name><spirit:envIdentifier>:*Synthesis:*</spirit:envIdentifier>
       <spirit:language>Verilog</spirit:language>
       <spirit:fileSetRef><spirit:localName>fs-syn</spirit:localName></spirit:fileSetRef>
       </spirit:view>


              <spirit:view>
              <spirit:name>doc</spirit:name>
              <spirit:vendorExtensions>
              <spirit:componentRef spirit:vendor="opencores.org" 
                                   spirit:library="Testbench" 
                                   spirit:name="toolflow" 
                                   spirit:version="documentation"/> 
              </spirit:vendorExtensions>
              <spirit:envIdentifier>:*Documentation:*</spirit:envIdentifier>
              <spirit:language>Verilog</spirit:language>
              </spirit:view>




      </spirit:views>



<spirit:modelParameters>
 <spirit:modelParameter><spirit:name>VEC_TABLE</spirit:name><spirit:value>8'hff</spirit:value></spirit:modelParameter>
 <spirit:modelParameter><spirit:name>BOOT_VEC</spirit:name><spirit:value>8'hfc</spirit:value></spirit:modelParameter>
</spirit:modelParameters>



<spirit:ports>   



<spirit:port><spirit:name>enable</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>



<spirit:port><spirit:name>nmi</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>

<spirit:port><spirit:name>vec_int</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction>
<spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>


<spirit:port><spirit:name>prog_data</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction>
<spirit:vector><spirit:left>15</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>


<spirit:port><spirit:name>pg0_data</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction>
<spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>

<spirit:port><spirit:name>alu_status</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction>
<spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>

<spirit:port><spirit:name>prog_counter</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction>
<spirit:vector><spirit:left>15</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>

<spirit:port><spirit:name>pg0_add</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction>
<spirit:vector><spirit:left>7</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>

<spirit:port><spirit:name>pg0_rd</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>

<spirit:port><spirit:name>pg0_wr</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>


<spirit:port><spirit:name>stk_push</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>

<spirit:port><spirit:name>stk_push_data</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction>
<spirit:vector><spirit:left>15</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>

<spirit:port><spirit:name>stk_pull</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>

<spirit:port><spirit:name>stk_pull_data</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction>
<spirit:vector><spirit:left>15</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>



</spirit:ports>

</spirit:model>    






</spirit:component>

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