OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [cpu/] [sim/] [testbenches/] [verilog/] [top.rtl] - Rev 135

Go to most recent revision | Compare with Previous | Blame | View Log





//=============================================================================
//    Rtl Glue Logic
//============================================================================= 
        

   assign pg0_data      =   pg0_add[0]?mem_rdata[15:8]:mem_rdata[7:0];
   assign pg00_ram_rd   =   pg0_rd||(mem_cs && rd);
   assign pg00_ram_l_wr =  (pg0_wr||(mem_cs && wr)) && (!pg0_add[0]);
   assign pg00_ram_h_wr =  (pg0_wr||(mem_cs && wr)) && ( pg0_add[0]);



Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.