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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [icarus/] [jfifo_sync/] [test_define] - Rev 133

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reg actual;
reg [31:0] d;

parameter       EXTEST=4'b0000;
parameter       SAMPLE=4'b0001;
parameter       HIGHZ_MODE=4'b0010;
parameter       CHIP_ID_ACCESS=4'b0011;
parameter       CLAMP=4'b1000;
parameter       RPC_DATA=4'b1010;
parameter       RPC_ADD=4'b1001;
parameter       BYPASS=4'b1111;
parameter       INST_RETURN=4'b1101;

initial
begin
$display("              ");
$display("              ===================================================");
$display("              Test Start");
$display("              ===================================================");
$display("              ");
test.cg.next(2);
test.jtag_model.enable_tclk; 
test.cg.next(20);
fork
begin
test.cg.next(20);
test.mask_jsp_data_out = 8'hff;
test.cg.next(20);

while (test.biu_wr_strobe != 1'b1) test.cg.next(1);
test.mask_jsp_data_out = 8'h00;
while (test.biu_wr_strobe != 1'b0) test.cg.next(1);
test.exp_jsp_data_out = 8'hff;
test.mask_jsp_data_out = 8'hff;


while (test.biu_wr_strobe != 1'b1) test.cg.next(1);
test.mask_jsp_data_out = 8'h00;
while (test.biu_wr_strobe != 1'b0) test.cg.next(1);
test.exp_jsp_data_out = 8'h81;
test.mask_jsp_data_out = 8'hff;


while (test.biu_wr_strobe != 1'b1) test.cg.next(1);
test.mask_jsp_data_out = 8'h00;
while (test.biu_wr_strobe != 1'b0) test.cg.next(1);
test.exp_jsp_data_out = 8'h18;
test.mask_jsp_data_out = 8'hff;


while (test.biu_wr_strobe != 1'b1) test.cg.next(1);
test.mask_jsp_data_out = 8'h00;
while (test.biu_wr_strobe != 1'b0) test.cg.next(1);
test.exp_jsp_data_out = 8'hca;
test.mask_jsp_data_out = 8'hff;


while (test.biu_wr_strobe != 1'b1) test.cg.next(1);
test.mask_jsp_data_out = 8'h00;
while (test.biu_wr_strobe != 1'b0) test.cg.next(1);
test.exp_jsp_data_out = 8'h7e;
test.mask_jsp_data_out = 8'hff;


while (test.biu_wr_strobe != 1'b1) test.cg.next(1);
test.mask_jsp_data_out = 8'h00;
while (test.biu_wr_strobe != 1'b0) test.cg.next(1);
test.exp_jsp_data_out = 8'h99;
test.mask_jsp_data_out = 8'hff;


while (test.biu_wr_strobe != 1'b1) test.cg.next(1);
test.mask_jsp_data_out = 8'h00;
while (test.biu_wr_strobe != 1'b0) test.cg.next(1);
test.exp_jsp_data_out = 8'hcc;
test.mask_jsp_data_out = 8'hff;


while (test.biu_wr_strobe != 1'b1) test.cg.next(1);
test.mask_jsp_data_out = 8'h00;
while (test.biu_wr_strobe != 1'b0) test.cg.next(1);
test.exp_jsp_data_out = 8'h36;
test.mask_jsp_data_out = 8'hff;


end



begin
test.cg.next(20);
test.jtag_model.enable_trst_n; 
test.jtag_model.enable_reset; 
test.jtag_model.init; 
test.cg.next(10);
test.jtag_model.LoadTapInst(EXTEST,INST_RETURN);
test.cg.next(100);
test.jtag_model.LoadTapInst(CLAMP,INST_RETURN);

test.cg.next(100);
test.jtag_model.LoadTapInst(CHIP_ID_ACCESS,INST_RETURN);
test.jtag_model.Shift_Cmp_32(32'ha5a5a5a5,32'h12345678);


test.cg.next(100);
test.jtag_model.LoadTapInst(RPC_ADD,INST_RETURN);

//Shift_Cmp_42(42'h38000000000,42'h00000000000);

test.cg.next(5000);


Shift_Cmp_42(42'b0_11001010_00011000_10000001_11111111_0100_00001       ,42'h097a7b7c744);
Shift_Cmp_42(42'b0_00110110_11001100_10011001_01111110_0100_00001       ,42'h00000000004);


test.cg.next(5000);




test.cg.next(100);

test.jtag_model.LoadTapInst(BYPASS,INST_RETURN);

test.cg.next(100);
end


begin


test.cg.next(1000);


fork
  begin
  test.jsp_data_in <= 8'hc7;
  test.jsp_data_in_stb <= 1'b1;
  test.cg.next(2);
  test.jsp_data_in_stb <= 1'b0;
  end
  begin

  test.cg.next(1);
  end
join

test.cg.next(30);

fork
  begin
  test.jsp_data_in <= 8'hb7;
  test.jsp_data_in_stb <= 1'b1;
  test.cg.next(2);
  test.jsp_data_in_stb <= 1'b0;
  end
  begin

  test.cg.next(1);
  end
join

test.cg.next(30);


fork
  begin
  test.jsp_data_in <= 8'ha7;
  test.jsp_data_in_stb <= 1'b1;
  test.cg.next(2);
  test.jsp_data_in_stb <= 1'b0;
  end
  begin

  test.cg.next(1);
  end
join

test.cg.next(30);



fork
  begin
  test.jsp_data_in <= 8'h97;
  test.jsp_data_in_stb <= 1'b1;
  test.cg.next(2);
  test.jsp_data_in_stb <= 1'b0;
  end
  begin

  test.cg.next(1);
  end
join

test.cg.next(30);







end



join




test.cg.exit;
end





task automatic  Shift_Cmp_42;    // Initialize boundary register with outputs disabled
                         // This tasks starts at RT_IDLE and ends at SHIFT_DR

  parameter [15:0] LENGTH =  42;


  input [LENGTH:1]  Dataout;
  input [LENGTH:1]  DataExp;

  integer i;
      
  reg [LENGTH:1]  DataBack;

  begin
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR 
    for (i = 1; i <= LENGTH; i = i+1)
       test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);
    $display  ("%t  %m    Shift_data_register    wr-%h  exp-%h rd-%h    ",$realtime,Dataout,DataExp,DataBack  );

   if (DataBack  !== DataExp )
   begin
   test.cg.fail  (" Shift_cmp  receive error  ");
   end

    test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR 
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE
  end
endtask // ShiftRegister




task automatic  Shift_Cmp_25;    // Initialize boundary register with outputs disabled
                         // This tasks starts at RT_IDLE and ends at SHIFT_DR

  parameter [15:0] LENGTH =  25;


  input [LENGTH:1]  Dataout;
  input [LENGTH:1]  DataExp;

  integer i;
      
  reg [LENGTH:1]  DataBack;

  begin
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR 
    for (i = 1; i <= LENGTH; i = i+1)
       test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);
    $display  ("%t  %m    Shift_data_register    wr-%h  exp-%h rd-%h    ",$realtime,Dataout,DataExp,DataBack  );

   if (DataBack  !== DataExp )
   begin
   test.cg.fail  (" Shift_cmp  receive error  ");
   end

    test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR 
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE
  end
endtask // ShiftRegister




task automatic  Shift_Cmp_34;    // Initialize boundary register with outputs disabled
                         // This tasks starts at RT_IDLE and ends at SHIFT_DR

  parameter [15:0] LENGTH =  34;


  input [LENGTH:1]  Dataout;
  input [LENGTH:1]  DataExp;

  integer i;
      
  reg [LENGTH:1]  DataBack;

  begin
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR 
    for (i = 1; i <= LENGTH; i = i+1)
       test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);
    $display  ("%t  %m    Shift_data_register    wr-%h  exp-%h rd-%h    ",$realtime,Dataout,DataExp,DataBack  );

   if (DataBack  !== DataExp )
   begin
   test.cg.fail  (" Shift_cmp  receive error  ");
   end

    test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR 
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE
  end
endtask // ShiftRegister





task automatic  Shift_Cmp_26;    // Initialize boundary register with outputs disabled
                         // This tasks starts at RT_IDLE and ends at SHIFT_DR

  parameter [15:0] LENGTH =  26;


  input [LENGTH:1]  Dataout;
  input [LENGTH:1]  DataExp;

  integer i;
      
  reg [LENGTH:1]  DataBack;

  begin
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR 
    for (i = 1; i <= LENGTH; i = i+1)
       test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);
    $display  ("%t  %m    Shift_data_register    wr-%h  exp-%h rd-%h    ",$realtime,Dataout,DataExp,DataBack  );

   if (DataBack  !== DataExp )
   begin
   test.cg.fail  (" Shift_cmp  receive error  ");
   end

    test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR 
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE
  end
endtask // ShiftRegister






task automatic  Shift_Cmp_17;    // Initialize boundary register with outputs disabled
                         // This tasks starts at RT_IDLE and ends at SHIFT_DR

  parameter [15:0] LENGTH =  17;


  input [LENGTH:1]  Dataout;
  input [LENGTH:1]  DataExp;

  integer i;
      
  reg [LENGTH:1]  DataBack;

  begin
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR 
    for (i = 1; i <= LENGTH; i = i+1)
       test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);
    $display  ("%t  %m    Shift_data_register    wr-%h  exp-%h rd-%h    ",$realtime,Dataout,DataExp,DataBack  );

   if (DataBack  !== DataExp )
   begin
   test.cg.fail  (" Shift_cmp  receive error  ");
   end

    test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR 
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE
  end
endtask // ShiftRegister




task automatic  Shift_Cmp_9;    // Initialize boundary register with outputs disabled
                         // This tasks starts at RT_IDLE and ends at SHIFT_DR

  parameter [15:0] LENGTH =  9;


  input [LENGTH:1]  Dataout;
  input [LENGTH:1]  DataExp;

  integer i;
      
  reg [LENGTH:1]  DataBack;

  begin
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR 
    for (i = 1; i <= LENGTH; i = i+1)
       test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);
    $display  ("%t  %m    Shift_data_register    wr-%h  exp-%h rd-%h    ",$realtime,Dataout,DataExp,DataBack  );

   if (DataBack  !== DataExp )
   begin
   test.cg.fail  (" Shift_cmp  receive error  ");
   end

    test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR 
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE
  end
endtask // ShiftRegister

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