URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [testbenches/] [verilog/] [tb.jfifo_sync] - Rev 131
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assign wb_clk_i = clk;
assign wb_jsp_dat_i = {jsp_data_in,jsp_data_in,jsp_data_in,jsp_data_in};
assign wb_jsp_stb_i = jsp_data_in_stb;
reg [7:0] jsp_data_in ;
reg jsp_data_in_stb ;
reg [7:0] exp_jsp_data_out ;
reg [7:0] mask_jsp_data_out;
io_probe_in
#(.MESG ("jsp_data_out Error"),
.WIDTH (8)
)
rdata_tpb
(
.clk ( clk ),
.expected_value ( exp_jsp_data_out ),
.mask ( mask_jsp_data_out ),
.signal ( jsp_data_out )
);
initial
begin
exp_jsp_data_out <= 8'h00;
mask_jsp_data_out <= 8'h00;
jsp_data_in <= 8'h00;
jsp_data_in_stb <= 1'b0;
end
assign rst_i = test_logic_reset_o;
assign tdo_i[0] = tdo_o;
assign tdo_i[1] = 1'b0;
assign bsr_tdo_i = 1'b0;
assign tck_i = syn_clk;
assign capture_dr_i = syn_capture_dr;
assign shift_dr_i = syn_shift_dr;
assign update_dr_i = syn_update_dr;
assign debug_select_i = syn_select[0];
assign tdi_i = syn_tdi_o;
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