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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [testbenches/] [verilog/] [tb.wb] - Rev 131

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assign wb_clk_i   = clk;
assign wb_rst_i   = reset;
assign wb_err_i   = 1'b0;
assign tck_i          = jtag_clk;
assign capture_dr_i   = capture_dr_o;
assign shift_dr_i     = shift_dr_o;
assign update_dr_i    = update_dr_o;
assign debug_select_i = select_o[0];
assign rst_i          = test_logic_reset_o;
assign tdo_i[0]       = tdo_o;
assign tdo_i[1]       = 1'b0;
assign bsr_tdo_i      = 1'b0;
assign tdi_i          = tdi_o;


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