Subversion Repositories socgen

<?xml version="1.0" encoding="UTF-8"?>
<!--
//                                                                        //
// Author : John Eaton  Ouabache Designworks                              //
//                                                                        //
//   Copyright (C) 2010 Authors and OPENCORES.ORG                         //
//                                                                        //
//   This source file may be used and distributed without                 //
//   restriction provided that this copyright statement is not            //
//   removed from the file and that any derivative work contains          //
//   the original copyright notice and the associated disclaimer.         //
//                                                                        //
//   This source file is free software; you can redistribute it           //
//   and/or modify it under the terms of the GNU Lesser General           //
//   Public License as published by the Free Software Foundation;         //
//   either version 2.1 of the License, or (at your option) any           //
//   later version.                                                       //
//                                                                        //
//   This source is distributed in the hope that it will be               //
//   useful, but WITHOUT ANY WARRANTY; without even the implied           //
//   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR              //
//   PURPOSE. See the GNU Lesser General Public License for more          //
//   details.                                                             //
//                                                                        //
//   You should have received a copy of the GNU Lesser General            //
//   Public License along with this source; if not, download it           //
//   from http://www.opencores.org/lgpl.shtml                             //
//                                                                        //
-->
<spirit:design 
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">

<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>adv_debug_sys</spirit:library>
<spirit:name>adv_dbg_if</spirit:name>
<spirit:version>wb_bfm.design</spirit:version>  




<spirit:adHocConnections>



  <spirit:adHocConnection>
      <spirit:name>clk</spirit:name>
      <spirit:externalPortReference spirit:portRef="clk"/>
      <spirit:internalPortReference spirit:componentRef="wb_ram" spirit:portRef="clk_i"/>
    </spirit:adHocConnection>

  <spirit:adHocConnection>
      <spirit:name>reset</spirit:name>
      <spirit:externalPortReference spirit:portRef="reset"/>
      <spirit:internalPortReference spirit:componentRef="wb_ram" spirit:portRef="rst_i"/>
    </spirit:adHocConnection>





</spirit:adHocConnections>


 <spirit:interconnections>


    <spirit:interconnection>
      <spirit:name>wb</spirit:name>
      <spirit:activeInterface spirit:componentRef="wb_ram" spirit:busRef="wb">
          <spirit:portMaps>
          <spirit:portMap>
          <spirit:logicalPort><spirit:name>adr</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort><spirit:name>wb_adr_o</spirit:name>
          <spirit:wire><spirit:vector><spirit:left>31</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
          </spirit:physicalPort>
          </spirit:portMap>


          <spirit:portMap>
          <spirit:logicalPort><spirit:name>wdata</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort><spirit:name>wb_dat_o</spirit:name>
          <spirit:wire><spirit:vector><spirit:left>31</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
          </spirit:physicalPort>
          </spirit:portMap>


          <spirit:portMap>
          <spirit:logicalPort><spirit:name>rdata</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort><spirit:name>wb_dat_i</spirit:name>
          <spirit:wire><spirit:vector><spirit:left>31</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
          </spirit:physicalPort>
          </spirit:portMap>


          <spirit:portMap>
          <spirit:logicalPort><spirit:name>sel</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort><spirit:name>wb_sel_o</spirit:name>
          <spirit:wire><spirit:vector><spirit:left>wb_byte_lanes-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
          </spirit:physicalPort>
          </spirit:portMap>

          <spirit:portMap>
          <spirit:logicalPort><spirit:name>ack</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort><spirit:name>wb_ack_i</spirit:name>
          </spirit:physicalPort>
          </spirit:portMap>

          <spirit:portMap>
          <spirit:logicalPort><spirit:name>cyc</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort><spirit:name>wb_cyc_o</spirit:name>
          </spirit:physicalPort>
          </spirit:portMap>

          <spirit:portMap>
          <spirit:logicalPort><spirit:name>stb</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort><spirit:name>wb_stb_o</spirit:name>
          </spirit:physicalPort>
          </spirit:portMap>

          <spirit:portMap>
          <spirit:logicalPort><spirit:name>we</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort><spirit:name>wb_we_o</spirit:name>
          </spirit:physicalPort>
          </spirit:portMap>

          </spirit:portMaps>
      </spirit:activeInterface>


    </spirit:interconnection>










 </spirit:interconnections>





<spirit:componentInstances>


<spirit:componentInstance>
<spirit:instanceName>wb_ram</spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="wishbone" spirit:name="wb_memory" spirit:version="def" />
<spirit:configurableElementValues>
 <spirit:configurableElementValue spirit:referenceId="wb_addr_width">wb_addr_width</spirit:configurableElementValue>
 <spirit:configurableElementValue spirit:referenceId="dat_width">32</spirit:configurableElementValue>
 <spirit:configurableElementValue spirit:referenceId="adr_width">14</spirit:configurableElementValue>
 <spirit:configurableElementValue spirit:referenceId="mem_size">65536</spirit:configurableElementValue>
 <spirit:configurableElementValue spirit:referenceId="SRAM_MEM_0_FILE">"NONE"</spirit:configurableElementValue>
 <spirit:configurableElementValue spirit:referenceId="SRAM_MEM_1_FILE">"NONE"</spirit:configurableElementValue>
 <spirit:configurableElementValue spirit:referenceId="SRAM_MEM_2_FILE">"NONE"</spirit:configurableElementValue>
 <spirit:configurableElementValue spirit:referenceId="SRAM_MEM_3_FILE">"NONE"</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>







</spirit:componentInstances>
  

</spirit:design>