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T6502 Embedded Microprocessor==================================================================================The T6502 IP is a processor that uses most of MosTechnology M6502 processor instructionsand processor registers.It has been updated for a synthesized embedded design in a FGPA or ASIC.It differs from the original Mos6502 in the following ways1) Changed memory interface from asynchronous to synchronous.2) Number of clock cycles to execute instructions has changed3) Page Zero is fully filled with SRAM. Page zero is not usable as I/O spaceAn extended version is also avaiable. Before we can extend we must first remove some features that eitherdid not make sense at the time or made only made sense for a 40 pin part sitting in a sea or ttl parts.1) Remove Binary Coded Decimal mode. The D bit in the PSR does nothing.2) Moved stack from Page 01 into a seperate RAM. Stack size is now parameterized and only accessable viapushes and pulls.Removed the TSX and TXS commands. If you need to manipulate the stack pointer and stackdata then you really should get a more powerfull processor3) Replaced old interrupt/brk system with vectored interrupt. Masking is done externally and vectors provideas many interrupts as you like. PSR is not pushed on interrupt and rts/rti become one instruction4) Indirect addresses stored in page 00 MUST be aligned on even addresses. This is done by shifting apage zero indirect address bu one bit and using both page 00 and 01.5) Bit (5) of the PSR is now a run bit. Forcing it to 0 will halt the processor until the next reset/interrupt6) Added Debugging logic and error checking7) self modifying code is no longer supported. You must provide a single rom image with all executable codeHistory=========================================================================================This component is derived from the opencores t6507lp project.The original project checked in by Gabriel Oshiro Zardo and Samuel Nascimento Pagliariniwas a atari 2600 on a chip. This takes the t6507 portion and turns it into a fully functional updated 6502.Processor Model===============================================================================================+----------+| Acc | Accumulator (A)+----------+| X | X Index Register (X)+----------+| Y | Y Index Register (Y)+----------+----------+| PCH | PCL | Program Counter (PC)+----------+----------+| 00000001 | SP | Stack Pointer (SP)+----------+----------+| P | Processor Status Word (P)+----------+NV1BDIZC|||||||+---- Carry Flag 1 = True||||||+----- Zero Flag 1 = Result == 8'h00|||||+------ IRQ Disable 1 = Disable||||+------- Decimal Mode Not used|||+-------- Break Command 1 = In break routine||+--------- Run Mode 1 = Processor is running|+---------- Overflow Flag 1 = True+----------- Negative 1 = Negative NumberMemory Model===============================================================================================0000-00FF | Page Zero RAM0010-01FF | Stack RAM0200-FFF9 | Program and Data RAMFFFA | NMI Vector LowFFFB | NMI Vector HighFFFC | Boot Vector LowFFFD | Boot Vector HighFFFE | IRQ/BRK Vector LowFFFF | IRQ/BRK Vector HighDefinitions===============================================================================================Opcode Current Instruction byteNew_opcode Next Instruction byteOpc_Add Address of current instructionNext_Op_Add Address of next instruction byteOperand Data operandAddress Address of data operand if in memoryOffset Value added to Opc_Add if branch is takenPointer Address to store the address of data opeand if in memoryVector Address to store the Next_Op_AddInstruction Set===============================================================================================Inst Description Effect on flags-----------------------------------------------------------------------------------------------ADC Operand Add Acc to Operand with Carry NZCVSBC Operand Subract Operand from Acc with Borrow NZXVAND Operand Logical AND Acc and Operand NZCMP Operand Compare Acc with Operand NZCCPX Operand Compare X_index with Operand NZCCPY Operand Compare Y_index with Operand NZCEOR Operand Exclusive Or Acc with Operand NZLDA Operand Load Operand into Acc NZLDX Operand Load Operand into X_index NZLDY Operand Load Operand into Y_index NZORA Operand Logical Or Acc with Operand NZBIT Operand Bit Test Acc with operand Z67STA Address Store Acc @ address NONESTX Address Store X_Index @ address NONESTY Address Store Y_Index @ address NONEASL Operand Arithmetic Shift Left Operand into Carry NZCDEC Operand Decrement Operand NZINC Operand Incremement Operand NZDEX Decrement X Index NZINX Incremement X Index NZDEY Decrement Y Index NZINY Incremement Y Index NZLSR Operand Logical Shift Right Operand into Carry NZCROL Operand Rotate Left Operand thru Carry NZCROR Operand Rotate Right Operand thru Carry NZCNOP No Operation NONESEC Set Carry Flag 1 -> CSED Set Decimal Flag 1 -> DSEI Set Interrupt Flag 1 -> ICLC Clear Carry Flag 0 -> CCLD Clear Decimal Flag 0 -> DCLI Clear Interrupt Flag 0 -> ICLV Clear Overflow Flag 0 -> VTAX Transfer Acc into X_Index NZTAY Transfer Acc into Y_Index NZTXA Transfer X_Index into Acc NZTYA Transfer Y_Index into Acc NZBCC Offset Branch if C == 0 NONEBCS Offset Branch if C == 1 NONEBNE Offset Branch if Z == 0 NONEBEQ Offset Branch if Z == 1 NONEBVC Offset Branch if V == 0 NONEBVS Offset Branch if V == 1 NONEBPL Offset Branch if N == 0 NONEBMI Offset Branch if N == 1 NONEPLA Pull Acc from Stack NZPLP Pull PSR from Stack RESTOREPHA Push Acc onto Stack NONEPHP Push PSR onto Stack NONEJMP Next_Op_Add Jump to New Address NONEJMP Vector Jump to New Address found by vector NONEJSR Next_Op_Add Save PC+2 on stack and jump to New Address NONEBRK Save status and PC+1 on stack and jump to New Address set 1 -> BRTI Pull Status and PC from stack RESTOREDRTS Pull PC from stack NONEDefinitions===============================================================================================Opcode Current Instruction byteNew_opcode Next Instruction byteOpc_Add Address of current instructionNext_Op_Add Address of next instruction byteOperand Data operandAddress Address of data operand if in memoryOffset Value added to Opc_Add if branch is takenPointer Address to store the address of data opeand if in memoryVector Address to store the Next_Op_AddAddressing Modes===============================================================================================Immediate Read-----------------------------------------------------------------------------------------------------Operand is located in memory following the opcodeOpcode OperandAbsolute Read/Write/ReadModifyWrite-----------------------------------------------------------------------------------------------------16 bit address of operand is located in memory following opcode (low byte,high byte)Opcode Address_l,Address_hAbsolute Indexed Read/Write/ReadModifyWrite-----------------------------------------------------------------------------------------------------Operand is found by adding index value to 16 bit address following opcode.(no wraparound)Opcode Address_l,Address_hPage Zero Read/Write/ReadModifyWrite-----------------------------------------------------------------------------------------------------8 bit page zero address of operand is located in memory following opcode.Opcode Address_lPage Zero Indexed Read/Write/ReadModifyWrite-----------------------------------------------------------------------------------------------------Operand is found in page zero by adding index value to 8 bit address following opcode.(wraps around)Opcode Address_lPage Zero Indirect X Read/Write-----------------------------------------------------------------------------------------------------Operand address lower byte is read from the address found by adding X index value to 8 bit address following opcode andthe upper byte is read from the address found by adding X index value to 8 bit address plus 1 (no wraparound)Opcode Pointer_lPage Zero Indirect Y Read/Write-----------------------------------------------------------------------------------------------------8 bit page zero address containing a 16 bit address is located in memory following opcode. Y index is added to this address(no wraparound).Opcode Pointer_lImplied Read/Write/Read_Modify_Write-----------------------------------------------------------------------------------------------------Operand is specified in the OpcodeOpcodeBranch Read-----------------------------------------------------------------------------------------------------Opcode is followed by the relative offset for the branchOpcode OffsetStack StackRead/StackWrite-----------------------------------------------------------------------------------------------------Operation uses the StackOpcodeStack_Pointer-----------------------------------------------------------------------------------------------------Transfer between Stack_pointer and X indexOpcodeJump Absolute Read-----------------------------------------------------------------------------------------------------16 bit destination address follows opcodeOpcode Next_Op_add_l,Next_Op_add_hJump Indirect Read-----------------------------------------------------------------------------------------------------16 bit Address following opcode points to destination addressOpcode Vector_l, Vector_hJumpSub Absolute Read_Stackwrite-----------------------------------------------------------------------------------------------------16 bit destination address follows opcode. Return address is pushed on stackOpcode Next_Op_add_l,Next_Op_add_hBreak Read_Stackwrite-----------------------------------------------------------------------------------------------------Return address is pushed on stack and the IRQ vector is takenOpcodeReturn from Interrupt Read_Stackread-----------------------------------------------------------------------------------------------------PSR and Prog_counter are pulled from stackOpcodeReturn from Subroutine Read_Stackread-----------------------------------------------------------------------------------------------------Prog_counter is pulled from stackOpcodeInstruction Opcodes (hex)====================================================================================================ADC abs 6DADC abs,X 7DADC abs,Y 79ADC #n 69ADC zp 65ADC (zp,X) 61ADC zp,X 75ADC (zp),Y 71AND abs 2DAND abs,X 3DAND abs,Y 39AND #n 29AND zp 25AND (zp,X) 21AND zp,X 35AND (zp),Y 31ASL A 0AASL abs 0EASL abs,X 1EASL zp 06ASL zp,X 16BCC rel 90BCS rel B0BEQ rel F0BIT abs 2CBIT zp 24BMI rel 30BNE rel D0BPL rel 10BRK 00BVC rel 50BVS rel 70CLC 18CLD D8CLI 58CLV B8CMP abs CDCMP abs,X DDCMP abs,Y D9CMP #n C9CMP zp C5CMP (zp,X) C1CMP zp,X D5CMP (zp),Y D1CPX abs ECCPX #n E0CPX zp E4CPY abs CCCPY #n C0CPY zp C4DEC abs CEDEC abs,X DEDEC zp C6DEC zp,X D6DEX CADEY 88EOR abs 4DEOR abs,X 5DEOR abs,Y 59EOR #n 49EOR zp 45EOR (zp,X) 41EOR zp,X 55EOR (zp),Y 51INC abs EEINC abs,X FEINC zp E6INC zp,X F6INX E8INY C8JMP abs 4CJMP (abs) 6CJSR abs 20LDA abs ADLDA abs,X BDLDA abs,Y B9LDA #n A9LDA zp A5LDA (zp,X) A1LDA zp,X B5LDA (zp),Y B1LDX abs AELDX abs,Y BELDX #n A2LDX zp A6LDX zp,Y B6LDY abs ACLDY abs,X BCLDY #n A0LDY zp A4LDY zp,X B4LSR A 4ALSR abs 4ELSR abs,X 5ELSR zp 46LSR zp,X 56NOP EAORA abs 0DORA abs,X 1DORA abs,Y 19ORA #n 09ORA zp 05ORA (zp,X) 01ORA zp,X 15ORA (zp),Y 11PHA 48PHP 08PLA 68PLP 28ROL A 2AROL abs 2EROL abs,X 3EROL zp 26ROL zp,X 36ROR A 6AROR abs 6EROR abs,X 7EROR zp 66ROR zp,X 76RTI 40RTS 60SBC abs EDSBC abs,X FDSBC abs,Y F9SBC #n E9SBC zp E5SBC (zp,X) E1SBC zp,X F5SBC (zp),Y F1SEC 38SED F8SEI 78STA abs 8DSTA abs,X 9DSTA abs,Y 99STA zp 85STA (zp,X) 81STA zp,X 95STA (zp),Y 91STX abs 8ESTX zp 86STX zpy 96STY abs 8CSTY zp 84STY zp,X 94TAX AATAY A8TXA 8ATYA 98Instruction Decode======================================================================================================================================================// alu_mode`define alu_mode_add 3'b000`define alu_mode_and 3'b001`define alu_mode_orr 3'b010`define alu_mode_eor 3'b011`define alu_mode_sfl 3'b100`define alu_mode_sfr 3'b101`define alu_mode_afl 3'b110`define alu_mode_afr 3'b111// alu_op_a_sel`define alu_op_a_00 3'b000`define alu_op_a_acc 3'b001`define alu_op_a_x 3'b010`define alu_op_a_y 3'b011`define alu_op_a_ff 3'b100`define alu_op_a_psr 3'b101// alu_op_b_sel`define alu_op_b_00 2'b00`define alu_op_b_prog 2'b01`define alu_op_b_sp 2'b10`define alu_op_b_temp 2'b11// alu_op_b_inv 1=invert// alu_op_c_sel`define alu_op_c_00 2'b00`define alu_op_c_01 2'b01`define alu_op_c_cin 2'b10`define alu_op_c_xx 2'b11// alu_status_update`define alu_status_update_none 3'b000`define alu_status_update_nz 3'b001`define alu_status_update_nzc 3'b010`define alu_status_update_nzcv 3'b011`define alu_status_update_wr 3'b100`define alu_status_update_z67 3'b101`define alu_status_update_res 3'b110// dest`define dest_none 3'b000`define dest_alu_a 3'b001`define dest_alu_x 3'b010`define dest_alu_y 3'b011`define dest_mem 3'b100// ctrl`define ctrl_none 3'b000`define ctrl_jsr 3'b001`define ctrl_jmp 3'b010`define ctrl_jmp_ind 3'b011`define ctrl_brk 3'b100`define ctrl_rti 3'b101`define ctrl_rts 3'b110`define ctrl_branch 3'b111// cmd`define cmd_none 2'b00`define cmd_push_psr 2'b01`define cmd_push_pc 2'b10`define cmd_load_vec 2'b11// ins_type`define ins_type_none 2'b00`define ins_type_read 2'b01`define ins_type_write 2'b10`define ins_type_rmw 2'b11// idx_sel`define idx_sel_00 2'b00`define idx_sel_x 2'b01`define idx_sel_y 2'b10// branch_value// branch_enableImmediatealu alu alu alu aluop_a op_b op_b op_c status alu ins idx branch branchsrc src inv src update mode type sel value enable dest ctrl cmd------------------------------------------------------------------------------------------------------------------------------------------------------ADC #n | | alu_a prog 0 cin NZCV ADD R 0 00 00 A none noneAND #n | | alu_a prog 0 0 NZ AND R 0 00 00 A none noneCMP #n | | alu_a prog 1 1 NZC ADD R 0 00 00 0 none noneCPX #n | | alu_x prog 1 1 NZC ADD R 0 00 00 0 none noneCPY #n | | alu_y prog 1 1 NZC ADD R 0 00 00 0 none noneEOR #n | | alu_a prog 0 0 NZ EOR R 0 00 00 A none noneLDA #n | | 00 prog 0 0 NZ ADD R 0 00 00 A none noneLDX #n | | 00 prog 0 0 NZ ADD R 0 00 00 X none noneLDY #n | | 00 prog 0 0 NZ ADD R 0 00 00 Y none noneORA #n | | alu_a prog 0 0 NZ ORR R 0 00 00 A none noneSBC #n | | alu_a prog 1 cin NZXV ADD R 0 00 00 A none noneAbsolute------------------------------------------------------------------------------------------------------------------------------------------------------ADC abs | | alu_a temp 0 cin NZCV ADD R 0 00 00 A none noneAND abs | | alu_a temp 0 0 NZ AND R 0 00 00 A none noneBIT abs | | alu_a temp 0 0 Z67 AND R 0 00 00 0 none noneCMP abs | | alu_a temp 1 1 NZC ADD R 0 00 00 0 none noneCPX abs | | alu_x temp 1 1 NZC ADD R 0 00 00 0 none noneCPY abs | | alu_y temp 1 1 NZC ADD R 0 00 00 0 none noneEOR abs | | alu_a temp 0 0 NZ EOR R 0 00 00 A none noneLDA abs | | 00 temp 0 0 NZ ADD R 0 00 00 A none noneLDX abs | | 00 temp 0 0 NZ ADD R 0 00 00 X none noneLDY abs | | 00 temp 0 0 NZ ADD R 0 00 00 Y none noneORA abs | | alu_a temp 0 0 NZ ORR R 0 00 00 A none noneSBC abs | | alu_a temp 1 cin NZXV ADD R 0 00 00 A none noneSTA abs | | alu_a temp 0 0 NONE ADD W 0 00 00 M none noneSTX abs | | alu_x temp 0 0 NONE ADD W 0 00 00 M none noneSTY abs | | alu_y temp 0 0 NONE ADD W 0 00 00 M none noneASL abs | | 00 temp 0 0 NZC SFL RMW 0 00 00 M none noneDEC abs | | FF temp 0 0 NZ ADD RMW 0 00 00 M none noneINC abs | | 00 temp 0 1 NZ ADD RMW 0 00 00 M none noneLSR abs | | 00 temp 0 0 NZC SFR RMW 0 00 00 M none noneROL abs | | 00 temp 0 cin NZC SFL RMW 0 00 00 M none noneROR abs | | 00 temp 0 cin NZC SFR RMW 0 00 00 M none noneAbsolute indexed------------------------------------------------------------------------------------------------------------------------------------------------------ADC abs,X | | alu_a temp 0 cin NZCV ADD R X 00 00 A none noneAND abs,X | | alu_a temp 0 0 NZ AND R X 00 00 A none noneCMP abs,X | | alu_a temp 1 1 NZC ADD R X 00 00 0 none noneEOR abs,X | | alu_a temp 0 0 NZ EOR R X 00 00 A none noneLDA abs,X | | 00 temp 0 0 NZ ADD R X 00 00 A none noneLDY abs,X | | 00 temp 0 0 NZ ADD R X 00 00 Y none noneORA abs,X | | alu_a temp 0 0 NZ ORR R X 00 00 A none noneSBC abs,X | | alu_a temp 1 cin NZXV ADD R X 00 00 A none noneADC abs,Y | | alu_a temp 0 cin NZCV ADD R Y 00 00 A none noneAND abs,Y | | alu_a temp 0 0 NZ AND R Y 00 00 A none noneCMP abs,Y | | alu_a temp 1 1 NZC ADD R Y 00 00 0 none noneEOR abs,Y | | alu_a temp 0 0 NZ EOR R Y 00 00 A none noneLDA abs,Y | | 00 temp 0 0 NZ ADD R Y 00 00 A none noneLDX abs,Y | | 00 temp 0 0 NZ ADD R Y 00 00 X none noneORA abs,Y | | alu_a temp 0 0 NZ ORR R Y 00 00 A none noneSBC abs,Y | | alu_a temp 1 cin NZXV ADD R Y 00 00 A none noneSTA abs,X | | alu_a temp 0 0 NONE ADD W X 00 00 M none noneSTA abs,Y | | alu_a temp 0 0 NONE ADD W Y 00 00 M none noneASL abs,X | | 00 temp 0 0 NZC SFL RMW X 00 00 M none noneDEC abs,X | | FF temp 0 0 NZ ADD RMW X 00 00 M none noneINC abs,X | | 00 temp 0 1 NZ ADD RMW X 00 00 M none noneLSR abs,X | | 00 temp 0 0 NZC SFR RMW X 00 00 M none noneROL abs,X | | 00 temp 0 cin NZC SFL RMW X 00 00 M none noneROR abs,X | | 00 temp 0 cin NZC SFR RMW X 00 00 M none nonePage Zero------------------------------------------------------------------------------------------------------------------------------------------------------ADC zp | | alu_a temp 0 cin NZCV ADD R 0 00 00 A none noneAND zp | | alu_a temp 0 0 NZ AND R 0 00 00 A none noneBIT zp | | alu_a temp 0 0 Z67 AND R 0 00 00 0 none noneCMP zp | | alu_a temp 1 1 NZC ADD R 0 00 00 0 none noneCPX zp | | alu_x temp 1 1 NZC ADD R 0 00 00 0 none noneCPY zp | | alu_y temp 1 1 NZC ADD R 0 00 00 0 none noneEOR zp | | alu_a temp 0 0 NZ EOR R 0 00 00 A none noneLDA zp | | 00 temp 0 0 NZ ADD R 0 00 00 A none noneLDX zp | | 00 temp 0 0 NZ ADD R 0 00 00 X none noneLDY zp | | 00 temp 0 0 NZ ADD R 0 00 00 Y none noneORA zp | | alu_a temp 0 0 NZ ORR R 0 00 00 A none noneSBC zp | | alu_a temp 1 cin NZXV ADD R 0 00 00 A none noneSTA zp | | alu_a temp 0 0 NONE ADD W 0 00 00 M none noneSTX zp | | alu_x temp 0 0 NONE ADD W 0 00 00 M none noneSTY zp | | alu_y temp 0 0 NONE ADD W 0 00 00 M none noneASL zp | | 00 temp 0 0 NZC SFL RMW 0 00 00 M none noneDEC zp | | FF temp 0 0 NZ ADD RMW 0 00 00 M none noneINC zp | | 00 temp 0 1 NZ ADD RMW 0 00 00 M none noneLSR zp | | 00 temp 0 0 NZC SFR RMW 0 00 00 M none noneROL zp | | 00 temp 0 cin NZC SFL RMW 0 00 00 M none noneROR zp | | 00 temp 0 cin NZC SFR RMW 0 00 00 M none nonePage Zero indexed------------------------------------------------------------------------------------------------------------------------------------------------------ADC zp,X | | alu_a temp 0 cin NZCV ADD R X 00 00 A none noneAND zp,X | | alu_a temp 0 0 NZ AND R X 00 00 A none noneCMP zp,X | | alu_a temp 1 1 NZC ADD R X 00 00 0 none noneEOR zp,X | | alu_a temp 0 0 NZ EOR R X 00 00 A none noneLDA zp,X | | 00 temp 0 0 NZ ADD R X 00 00 A none noneLDY zp,X | | 00 temp 0 0 NZ ADD R X 00 00 Y none noneORA zp,X | | alu_a temp 0 0 NZ ORR R X 00 00 A none noneSBC zp,X | | alu_a temp 1 cin NZXV ADD R X 00 00 A none noneLDX zp,Y | | 00 temp 0 0 NZ ADD R Y 00 00 X none noneSTA zp,X | | alu_a temp 0 0 NONE ADD W X 00 00 M none noneSTY zp,X | | alu_y temp 0 0 NONE ADD W X 00 00 M none noneSTX zp,Y | | alu_x temp 0 0 NONE ADD W Y 00 00 M none noneASL zp,X | | 00 temp 0 0 NZC SFL RMW X 00 00 M none noneDEC zp,X | | FF temp 0 0 NZ ADD RMW X 00 00 M none noneINC zp,X | | 00 temp 0 1 NZ ADD RMW X 00 00 M none noneLSR zp,X | | 00 temp 0 0 NZC SFR RMW X 00 00 M none noneROR zp,X | | 00 temp 0 cin NZC SFR RMW X 00 00 M none noneROL zp,X | | 00 temp 0 cin NZC SFL RMW X 00 00 M none nonePage Zero indirectX------------------------------------------------------------------------------------------------------------------------------------------------------ADC (zp,X) | | alu_a temp 0 cin NZCV ADD R X 00 00 A none noneAND (zp,X) | | alu_a temp 0 0 NZ AND R X 00 00 A none noneCMP (zp,X) | | alu_a temp 1 1 NZC ADD R X 00 00 0 none noneEOR (zp,X) | | alu_a temp 0 0 NZ EOR R X 00 00 A none noneLDA (zp,X) | | 00 temp 0 0 NZ ADD R X 00 00 A none noneORA (zp,X) | | alu_a temp 0 0 NZ ORR R X 00 00 A none noneSBC (zp,X) | | alu_a temp 1 cin NZXV ADD R X 00 00 A none noneSTA (zp,X) | | alu_a temp 0 0 NONE ADD W X 00 00 M none none======================================================================================================================================================Page Zero IndirectY------------------------------------------------------------------------------------------------------------------------------------------------------ADC (zp),Y | | alu_a temp 0 cin NZCV ADD R Y 00 00 A none noneAND (zp),Y | | alu_a temp 0 0 NZ AND R Y 00 00 A none noneCMP (zp),Y | | alu_a temp 1 1 NZC ADD R Y 00 00 0 none noneEOR (zp),Y | | alu_a temp 0 0 NZ EOR R Y 00 00 A none noneLDA (zp),Y | | 00 temp 0 0 NZ ADD R Y 00 00 A none noneORA (zp),Y | | alu_a temp 0 0 NZ ORR R Y 00 00 A none noneSBC (zp),Y | | alu_a temp 1 cin NZXV ADD R Y 00 00 A none noneSTA (zp),Y | | alu_a temp 0 0 NONE ADD W Y 00 00 M none noneImplied------------------------------------------------------------------------------------------------------------------------------------------------------NOP | | 00 00 0 0 NONE ADD 0 0 00 00 0 none noneSEC | | 00 00 0 0 WR ADD 0 0 01 01 0 none noneSED | | 00 00 0 0 WR ADD 0 0 08 08 0 none noneSEI | | 00 00 0 0 WR ADD 0 0 04 04 0 none noneCLC | | 00 00 0 0 WR ADD 0 0 00 01 0 none noneCLD | | 00 00 0 0 WR ADD 0 0 00 08 0 none noneCLI | | 00 00 0 0 WR ADD 0 0 00 04 0 none noneCLV | | 00 00 0 0 WR ADD 0 0 00 40 0 none noneASL A | | alu_a 00 0 0 NZC SFL RMW 0 00 00 A none noneDEX | | alu_x 00 0 0 NZ ADD RMW 0 00 00 X none noneDEY | | alu_y 00 0 0 NZ ADD RMW 0 00 00 Y none noneINX | | alu_x 00 0 1 NZ ADD RMW 0 00 00 X none noneINY | | alu_y 00 0 1 NZ ADD RMW 0 00 00 Y none noneLSR A | | alu_a 00 0 0 NZC SFR RMW 0 00 00 A none noneROL A | | alu_a 00 0 cin NZC SFL RMW 0 00 00 A none noneROR A | | alu_a 00 0 cin NZC SFR RMW 0 00 00 A none noneTAX | | alu_a 00 0 0 NZ ADD RMW 0 00 00 A none noneTAY | | alu_a 00 0 0 NZ ADD RMW 0 00 00 X none noneTXA | | alu_x 00 0 0 NZ ADD RMW 0 00 00 A none noneTYA | | alu_y 00 0 0 NZ ADD RMW 0 00 00 A none noneBranchalu alu alu alu aluop_a op_b op_b op_c status alu branch branchsrc src inv src update mode type index value enable dest------------------------------------------------------------------------------------------------------------------------------------------------------BCC rel | | 00 00 0 0 NONE ADD 0 0 00 01 0 branch noneBCS rel | | 00 00 0 0 NONE ADD 0 0 01 01 0 branch noneBNE rel | | 00 00 0 0 NONE ADD 0 0 00 02 0 branch noneBEQ rel | | 00 00 0 0 NONE ADD 0 0 02 02 0 branch noneBVC rel | | 00 00 0 0 NONE ADD 0 0 00 40 0 branch noneBVS rel | | 00 00 0 0 NONE ADD 0 0 40 40 0 branch noneBPL rel | | 00 00 0 0 NONE ADD 0 0 00 80 0 branch noneBMI rel | | 00 00 0 0 NONE ADD 0 0 80 80 0 branch noneStack------------------------------------------------------------------------------------------------------------------------------------------------------PLA | | 00 00 0 0 NZ ADD R 0 00 00 APLP | | 00 00 0 0 RESTORE ADD R 0 00 00 PSRPHA | | alu_a 00 0 0 NONE ADD W 0 00 00 MPHP | | psr 00 0 0 NONE ADD W 0 00 00 MJump absolute------------------------------------------------------------------------------------------------------------------------------------------------------JMP abs | | 00 00 0 0 NONE ADD 0 0 00 00 0Jump indirect------------------------------------------------------------------------------------------------------------------------------------------------------JMP (abs) | | 00 00 0 0 NONE ADD 0 0 00 00 0Jump Sub absolute------------------------------------------------------------------------------------------------------------------------------------------------------JSR abs | | 00 00 0 0 NONE ADD 0 0 00 00 0Break------------------------------------------------------------------------------------------------------------------------------------------------------BRK | | alu_a 00 0 0 WR ADD 0 0 10 10 0Return fromInterrupt------------------------------------------------------------------------------------------------------------------------------------------------------RTI | | 00 00 0 0 RESTORE ADD 0 0 00 00 PReturn fromSubroutine------------------------------------------------------------------------------------------------------------------------------------------------------RTS | | 00 00 0 0 NONE ADD 0 0 00 00 0Opcode Current Instruction byteNew_opcode Next Instruction byteOpc_Add Address of current instructionNext_Op_Add Address of next instruction byteOperand Data operandAddress Address of data operand if in memoryOffset Value added to Opc_Add if branch is takenPointer Address to store the address of data opeand if in memoryVector Address to store the Next_Op_AddAddress Sequence Decodes=========================================================================Implied Addressing Modec e ALUl n prog prog prog data memory page zero stack Control Processsork b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers______________________________________________________________________________________________________________________________________0 0 Opc_Add1 1 Opc_Add Opcode opcode--------------------------------------------------------------------------------------------------------------------------------------2 0 Opc_Add+1 Opcode 1 Set3 1 Opc_Add+1 New_Opcode opcode 1 Set--------------------------------------------------------------------------------------------------------------------------------------4 0 Opc_Add+2 New_Opcode updatedImmediate Addressing Modec e ALUl n prog prog prog data memory page zero stack Control Processsork b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers____________________________________________________________________________________________________________________________________________________________0 0 Opc_Add1 1 Opc_Add opcode opcode----------------------------------------------------------------------------------------------------------------------------------------------------2 0 Opc_Add+1 opcode Set3 1 Opc_Add+1 operand operand Set----------------------------------------------------------------------------------------------------------------------------------------------------4 0 Opc_Add+2 operand 1 Set5 1 Opc_Add+2 new_op opcode 1 Set----------------------------------------------------------------------------------------------------------------------------------------------------6 0 Opc_Add+3 new_op updatedAbsolute Read Addressing Modec e ALUl n prog prog prog data memory page zero stack Control Processsork b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers___________________________________________________________________________________________________________________________________________________________0 0 Opc_Add1 1 Opc_Add opcode opcode--------------------------------------------------------------------------------------------------------------------------------------------2 0 Opc_Add+1 opcode Set3 1 Opc_Add+2 add_lo add_lo Set--------------------------------------------------------------------------------------------------------------------------------------------4 0 Opc_Add+3 add_hi add_hi Set5 1 Opc_Add+3 new_op addr r 00 Set--------------------------------------------------------------------------------------------------------------------------------------------6 0 Opc_Add+3 new_op addr r 00 operand Set7 1 Opc_Add+3 new_op addr r 00 operand Set--------------------------------------------------------------------------------------------------------------------------------------------8 0 Opc_Add+3 new_op 1 Set9 1 Opc_Add+3 new_op opcode 1 Set--------------------------------------------------------------------------------------------------------------------------------------------10 0 updatedAbsolute Write Addressing Modec e ALUl n prog prog prog data memory page zero stack Control Processsork b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers___________________________________________________________________________________________________________________________________________________________0 0 Opc_Add1 1 Opc_Add opcode opcode--------------------------------------------------------------------------------------------------------------------------------------------2 0 Opc_Add+1 opcode Set3 1 Opc_Add+2 add_lo add_lo Set--------------------------------------------------------------------------------------------------------------------------------------------4 0 Opc_Add+3 add_hi add_hi Set5 1 Opc_Add+3 new_op opcode addr w operand 1 Set--------------------------------------------------------------------------------------------------------------------------------------------6 0 Opc_Add+4 new_op updated7 1 Opc_Add+4Absolute Read/Modify/Write Addressing Modec e ALUl n prog prog prog data memory page zero stack Control Processsork b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers___________________________________________________________________________________________________________________________________________________________0 0 Opc_Add1 1 Opc_Add opcode opcode--------------------------------------------------------------------------------------------------------------------------------------------2 0 Opc_Add+1 opcode Set3 1 Opc_Add+2 add_lo add_lo Set--------------------------------------------------------------------------------------------------------------------------------------------4 0 Opc_Add+3 add_hi add_hi Set5 1 Opc_Add+3 new_op addr r Set--------------------------------------------------------------------------------------------------------------------------------------------6 0 Opc_Add+3 new_op operand Set7 1 Opc_Add+3 new_op Set--------------------------------------------------------------------------------------------------------------------------------------------8 0 Opc_Add+3 new_op addr w result 1 Set9 1 Opc_Add+3 new_op opcode 1 Set--------------------------------------------------------------------------------------------------------------------------------------------10 0 updatedAbsolute Indexed Read Addressing Modec e ALUl n prog prog prog data memory page zero stack Control Processsork b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers___________________________________________________________________________________________________________________________________________________________0 0 Opc_Add1 1 Opc_Add opcode opcode--------------------------------------------------------------------------------------------------------------------------------------------2 0 Opc_Add+1 opcode Set3 1 Opc_Add+2 add_lo add_lo Set--------------------------------------------------------------------------------------------------------------------------------------------4 0 Opc_Add+3 add_hi add_hi Set5 1 Opc_Add+3 new_op addr+i r 00 Set--------------------------------------------------------------------------------------------------------------------------------------------6 0 Opc_Add+3 new_op addr+i r 00 operand Set7 1 Opc_Add+3 new_op addr+i r 00 operand Set--------------------------------------------------------------------------------------------------------------------------------------------8 0 Opc_Add+3 new_op 1 Set9 1 Opc_Add+3 new_op opcode 1 Set--------------------------------------------------------------------------------------------------------------------------------------------10 0 updatedAbsolute Indexed Write Addressing Modec e ALUl n prog prog prog data memory page zero stack Control Processsork b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers___________________________________________________________________________________________________________________________________________________________0 0 Opc_Add1 1 Opc_Add opcode opcode--------------------------------------------------------------------------------------------------------------------------------------------2 0 Opc_Add+1 opcode Set3 1 Opc_Add+2 add_lo add_lo Set--------------------------------------------------------------------------------------------------------------------------------------------4 0 Opc_Add+3 add_hi add_hi 1 Set5 1 Opc_Add+3 new_op opcode addr+i w operand 1 Set--------------------------------------------------------------------------------------------------------------------------------------------6 0 Opc_Add+4 new_op updated7 1 Opc_Add+4Absolute Indexed Read/Modify/Write Addressing Modec e ALUl n prog prog prog data memory page zero stack Control Processsork b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers___________________________________________________________________________________________________________________________________________________________0 0 Opc_Add1 1 Opc_Add opcode opcode--------------------------------------------------------------------------------------------------------------------------------------------2 0 Opc_Add+1 opcode Set3 1 Opc_Add+2 add_lo add_lo Set--------------------------------------------------------------------------------------------------------------------------------------------4 0 Opc_Add+3 add_hi add_hi Set5 1 Opc_Add+3 new_op addr+i r Set--------------------------------------------------------------------------------------------------------------------------------------------6 0 Opc_Add+3 new_op operand Set7 1 Opc_Add+3 new_op Set--------------------------------------------------------------------------------------------------------------------------------------------8 0 Opc_Add+3 new_op addr+i w result 1 Set9 1 Opc_Add+3 new_op opcode 1 Set--------------------------------------------------------------------------------------------------------------------------------------------10 0 updatedPage Zero Read Addressing Modec e ALUl n prog prog prog data memory page zero stack Control Processsork b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers___________________________________________________________________________________________________________________________________________________________0 0 Opc_Add1 1 Opc_Add opcode opcode--------------------------------------------------------------------------------------------------------------------------------------------2 0 Opc_Add+1 opcode Set3 1 Opc_Add+1 add_lo add_lo Set--------------------------------------------------------------------------------------------------------------------------------------------4 0 Opc_Add+2 add_lo addr r Set5 1 Opc_Add+2 new_op operand Set--------------------------------------------------------------------------------------------------------------------------------------------6 0 Opc_Add+2 new_op 1 Set7 1 Opc_Add+2 new_op opcode 1 Set--------------------------------------------------------------------------------------------------------------------------------------------8 0 Opc_Add+3 new_op updatedPage Zero Write Addressing Modec e ALUl n prog prog prog data memory page zero stack Control Processsork b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers___________________________________________________________________________________________________________________________________________________________0 0 Opc_Add1 1 Opc_Add opcode opcode--------------------------------------------------------------------------------------------------------------------------------------------2 0 Opc_Add+1 opcode Set3 1 Opc_Add+1 add_lo add_lo Set--------------------------------------------------------------------------------------------------------------------------------------------4 0 Opc_Add+2 add_lo 1 Set5 1 Opc_Add+2 new_op opcode addr w operand 1 Set--------------------------------------------------------------------------------------------------------------------------------------------6 0 Opc_Add+3 new_op updated7 1 Opc_Add+3Page Zero Read/Modify/Write Addressing Modec e ALUl n prog prog prog data memory page zero stack Control Processsork b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers___________________________________________________________________________________________________________________________________________________________0 0 Opc_Add1 1 Opc_Add opcode opcode--------------------------------------------------------------------------------------------------------------------------------------------2 0 Opc_Add+1 opcode Set3 1 Opc_Add+1 add_lo add_lo Set--------------------------------------------------------------------------------------------------------------------------------------------4 0 Opc_Add+2 add_lo addr r Set5 1 Opc_Add+2 new_op operand Set--------------------------------------------------------------------------------------------------------------------------------------------6 0 Opc_Add+2 new_op 1 Set7 1 Opc_Add+2 new_op opcode addr w result 1 Set--------------------------------------------------------------------------------------------------------------------------------------------8 0 Opc_Add+3 new_op updatedPage Zero Indexed Read Addressing Modec e ALUl n prog prog prog data memory page zero stack Control Processsork b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers___________________________________________________________________________________________________________________________________________________________0 0 Opc_Add1 1 Opc_Add opcode opcode--------------------------------------------------------------------------------------------------------------------------------------------2 0 Opc_Add+1 opcode Set3 1 Opc_Add+1 add_lo add_lo Set--------------------------------------------------------------------------------------------------------------------------------------------4 0 Opc_Add+2 add_lo addr+i r Set5 1 Opc_Add+2 new_op operand Set--------------------------------------------------------------------------------------------------------------------------------------------6 0 Opc_Add+2 new_op 1 Set7 1 Opc_Add+2 new_op opcode 1 Set--------------------------------------------------------------------------------------------------------------------------------------------8 0 Opc_Add+3 new_op updatedPage Zero Indexed Write Addressing Modec e ALUl n prog prog prog data memory page zero stack Control Processsork b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers___________________________________________________________________________________________________________________________________________________________0 0 Opc_Add1 1 Opc_Add opcode opcode--------------------------------------------------------------------------------------------------------------------------------------------2 0 Opc_Add+1 opcode Set3 1 Opc_Add+1 add_lo add_lo Set--------------------------------------------------------------------------------------------------------------------------------------------4 0 Opc_Add+2 add_lo 1 Set5 1 Opc_Add+2 new_op opcode addr w operand 1 Set--------------------------------------------------------------------------------------------------------------------------------------------6 0 Opc_Add+3 new_op updated7 1 Opc_Add+3Page Zero Indexed Read/Modify/Write Addressing Modec e ALUl n prog prog prog data memory page zero stack Control Processsork b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers___________________________________________________________________________________________________________________________________________________________0 0 Opc_Add1 1 Opc_Add opcode opcode--------------------------------------------------------------------------------------------------------------------------------------------2 0 Opc_Add+1 opcode Set3 1 Opc_Add+1 add_lo add_lo Set--------------------------------------------------------------------------------------------------------------------------------------------4 0 Opc_Add+2 add_lo addr r Set5 1 Opc_Add+2 new_op operand Set--------------------------------------------------------------------------------------------------------------------------------------------6 0 Opc_Add+2 new_op 1 Set7 1 Opc_Add+2 new_op opcode addr w result 1 Set--------------------------------------------------------------------------------------------------------------------------------------------8 0 Opc_Add+3 new_op updatedPage Zero Indirect X Read-------------------------------------------------------Operand address lower byte is read from the address found by adding X index value to 8 bit address following opcode andthe upper byte is read from the address found by adding X index value to 8 bit address plus 1 (no wraparound)Page Zero IndirectX Read Addressing Modec e ALUl n prog prog prog data memory page zero stack Control Processsork b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers___________________________________________________________________________________________________________________________________________________________0 0 Opc_Add1 1 Opc_Add opcode opcode--------------------------------------------------------------------------------------------------------------------------------------------2 0 Opc_Add+1 opcode Set3 1 Opc_Add+1 add_lo add_lo Set--------------------------------------------------------------------------------------------------------------------------------------------4 0 Opc_Add+2 add_lo addr+i r Set5 1 Opc_Add+2 new_op addr+i+1 r add_l Set--------------------------------------------------------------------------------------------------------------------------------------------6 0 Opc_Add+2 new_op add_h Set7 1 Opc_Add+2 new_op addr r Set--------------------------------------------------------------------------------------------------------------------------------------------8 0 Opc_Add+2 new_op operand 1 Set9 1 opcode 1 Set--------------------------------------------------------------------------------------------------------------------------------------------10 0 updatedPage Zero IndirectX Write Addressing Modec e ALUl n prog prog prog data memory page zero stack Control Processsork b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers___________________________________________________________________________________________________________________________________________________________0 0 Opc_Add1 1 Opc_Add opcode opcode--------------------------------------------------------------------------------------------------------------------------------------------2 0 Opc_Add+1 opcode Set3 1 Opc_Add+1 add_lo add_lo Set--------------------------------------------------------------------------------------------------------------------------------------------4 0 Opc_Add+2 add_lo addr+i r Set5 1 Opc_Add+2 new_op addr+i+1 add_l Set--------------------------------------------------------------------------------------------------------------------------------------------6 0 Opc_Add+2 new_op add_h 1 Set7 1 Opc_Add+2 new_op opcode addr w result 1 Set--------------------------------------------------------------------------------------------------------------------------------------------8 0 Opc_Add+3 new_op updated9 1Page Zero IndirectY Read Addressing Modec e ALUl n prog prog prog data memory page zero stack Control Processsork b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers___________________________________________________________________________________________________________________________________________________________0 0 Opc_Add1 1 Opc_Add opcode opcode--------------------------------------------------------------------------------------------------------------------------------------------2 0 Opc_Add+1 opcode Set3 1 Opc_Add+1 add_lo add_lo Set--------------------------------------------------------------------------------------------------------------------------------------------4 0 Opc_Add+2 add_lo addr_lo r Set5 1 Opc_Add+2 new_op addr Set--------------------------------------------------------------------------------------------------------------------------------------------6 0 Opc_Add+2 new_op addr+i r Set7 1 Opc_Add+2 new_op addr+i r operand Set--------------------------------------------------------------------------------------------------------------------------------------------8 0 Opc_Add+2 new_op 1 Set9 1 opcode 1 Set--------------------------------------------------------------------------------------------------------------------------------------------10 0 updatedPage Zero IndirectX Write Addressing Modec e ALUl n prog prog prog data memory page zero stack Control Processsork b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers___________________________________________________________________________________________________________________________________________________________0 0 Opc_Add1 1 Opc_Add opcode opcode--------------------------------------------------------------------------------------------------------------------------------------------2 0 Opc_Add+1 opcode Set3 1 Opc_Add+1 add_lo add_lo Set--------------------------------------------------------------------------------------------------------------------------------------------4 0 Opc_Add+2 add_lo add_lo r 1 Set5 1 Opc_Add+2 new_op addr 1 Set--------------------------------------------------------------------------------------------------------------------------------------------6 0 Opc_Add+2 new_op addr+i w result Set7 1 Opc_Add+2 new_op opcode Set updated--------------------------------------------------------------------------------------------------------------------------------------------8 0 Opc_Add+3 new_op9 1Relative Addressing Modec e ALUl n prog prog prog data memory page zero stack Control Processsork b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers____________________________________________________________________________________________________________________________________________________________0 0 Opc_Add1 1 Opc_Add opcode opcode----------------------------------------------------------------------------------------------------------------------------------------------------2 0 Opc_Add+1 opcode Set3 1 Opc_Add+1 offset offset Set----------------------------------------------------------------------------------------------------------------------------------------------------4 0 Next_Op_Add offset 15 1 Next_Op_Add new_op opcode 1----------------------------------------------------------------------------------------------------------------------------------------------------6 0 Next_Op_Add+1 new_opAddressing Modes===============================================================================================Stack StackRead/StackWrite-------------------------------------------------------Operation uses the StackJump Absolute Read-------------------------------------------------------16 bit destination address follows opcodeJump Indirect Read-------------------------------------------------------16 bit Address following opcode points to destination addressJump Sub Absolute Read_Stackwrite-------------------------------------------------------16 bit destination address follows opcode. Return address is pushed on stackBreak Read_Stackwrite-------------------------------------------------------Return address is pushed on stack and the IRQ vector is takenReturn from Interrupt Read_Stackread-------------------------------------------------------PSR and Prog_counter are pulled from stackReturn from Subroutine Read_Stackread-------------------------------------------------------Prog_counter is pulled from stackInterrupts===============================================================================================Non-Maskable (NMI)1) Finish current instruction2) Push Address of next instruction on stack3) Read Vector Address from FFFA4) Execute code @ vector addressMaskable (IRQ) ( if I bit is clear)1) Finish current instruction2) Push Address of next instruction on stack3) Push PSR on stack4) Read Vector Address from FFFE5) Execute code @ vector addressReset1) Clear A,X,Y: Set PSR to 20h2) Wait for Reset to deassert3) Read Vector Address from FFFC4) Execute code @ vector address
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