Subversion Repositories socgen

<?xml version="1.0" encoding="UTF-8"?>
<!--
//                                                                        //
// Author : John Eaton  Ouabache Designworks                              //
//                                                                        //
//   Copyright (C) 2010 Authors and OPENCORES.ORG                         //
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//   This source file may be used and distributed without                 //
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//   This source file is free software; you can redistribute it           //
//   and/or modify it under the terms of the GNU Lesser General           //
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//   This source is distributed in the hope that it will be               //
//   useful, but WITHOUT ANY WARRANTY; without even the implied           //
//   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR              //
//   PURPOSE. See the GNU Lesser General Public License for more          //
//   details.                                                             //
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//   You should have received a copy of the GNU Lesser General            //
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-->
<spirit:component 
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">

<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>fpgas</spirit:library>
<spirit:name>Nexys2_T6502</spirit:name>
<spirit:version>core</spirit:version>  <spirit:configuration>default</spirit:configuration>  





<spirit:componentGenerators>

<spirit:componentGenerator>
  <spirit:name>gen_verilog</spirit:name>
  <spirit:phase>104.0</spirit:phase>
  <spirit:apiType>none</spirit:apiType>
  <spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
  <spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe>
  <spirit:parameters>
    <spirit:parameter> 
      <spirit:name>destination</spirit:name>
      <spirit:value>top.T6502</spirit:value>
    </spirit:parameter>
    <spirit:parameter> 
      <spirit:name>dest_dir</spirit:name>
      <spirit:value>../verilog</spirit:value>
    </spirit:parameter>
  </spirit:parameters>
</spirit:componentGenerator>










</spirit:componentGenerators>



<spirit:fileSets>

   <spirit:fileSet>
      <spirit:name>fs-common</spirit:name>


      <spirit:file>
        <spirit:logicalName></spirit:logicalName>
        <spirit:name>../verilog/top.jabc</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType>
      </spirit:file>


      <spirit:file>
        <spirit:logicalName></spirit:logicalName>
        <spirit:name>../verilog/top.gpio</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType>
      </spirit:file>



      <spirit:file>
        <spirit:logicalName></spirit:logicalName>
        <spirit:name>../verilog/top.rs_uart</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType>
      </spirit:file>

      <spirit:file>
        <spirit:name>../verilog</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
      </spirit:file>



   </spirit:fileSet>


   <spirit:fileSet>
      <spirit:name>fs-sim</spirit:name>

      <spirit:file>
        <spirit:logicalName></spirit:logicalName>
        <spirit:name>../verilog/copyright.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
      </spirit:file>

      <spirit:file>
        <spirit:logicalName></spirit:logicalName>
        <spirit:name>../verilog/common/top.T6502</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
      </spirit:file>




   </spirit:fileSet>





</spirit:fileSets>





   

<spirit:model>    
       <spirit:views>

              <spirit:view>
              <spirit:name>Hierarchical</spirit:name>
              
              <spirit:hierarchyRef spirit:vendor="opencores.org" 
                                   spirit:library="fpgas" 
                                   spirit:name="Nexys2_T6502" 
                                   spirit:version="core.design"/>
              </spirit:view>


              <spirit:view>
              <spirit:name>Core</spirit:name>
              
              <spirit:vendorExtensions>
              <spirit:componentRef spirit:vendor="digilentinc.com" 
                                   spirit:library="Nexys2" 
                                   spirit:name="fpga" 
                                   spirit:version="core"/>
              </spirit:vendorExtensions>


              </spirit:view>


              <spirit:view>
              <spirit:name>verilog</spirit:name>              
              <spirit:vendorExtensions>
              <spirit:componentRef spirit:vendor="opencores.org" 
                                   spirit:library="Testbench" 
                                   spirit:name="toolflow" 
                                   spirit:version="verilog"/> 
              </spirit:vendorExtensions>
              </spirit:view>





              <spirit:view>
              <spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier>
              <spirit:language>Verilog</spirit:language>
              <spirit:modelName></spirit:modelName>
                     <spirit:fileSetRef>
                            <spirit:localName>fs-common</spirit:localName>
                     </spirit:fileSetRef>
              </spirit:view>

              <spirit:view>
              <spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier>
              <spirit:language>Verilog</spirit:language>
              <spirit:modelName></spirit:modelName>
                     <spirit:fileSetRef>
                            <spirit:localName>fs-sim</spirit:localName>
                     </spirit:fileSetRef>
              </spirit:view>


              <spirit:view>
              <spirit:name>syn</spirit:name><spirit:envIdentifier>:*Synthesis:*</spirit:envIdentifier>
              <spirit:language>Verilog</spirit:language>
              <spirit:modelName></spirit:modelName>
                     <spirit:fileSetRef>
                            <spirit:localName>fs-sim</spirit:localName>
                     </spirit:fileSetRef>
              </spirit:view>





      </spirit:views>



<spirit:modelParameters>
 <spirit:modelParameter><spirit:name>RAM_WORDS</spirit:name><spirit:value>2048</spirit:value></spirit:modelParameter>
 <spirit:modelParameter><spirit:name>RAM_ADD</spirit:name><spirit:value>11</spirit:value></spirit:modelParameter>
 <spirit:modelParameter><spirit:name>ROM_WORDS</spirit:name><spirit:value>4096</spirit:value></spirit:modelParameter>
 <spirit:modelParameter><spirit:name>ROM_ADD</spirit:name><spirit:value>12</spirit:value></spirit:modelParameter>
 <spirit:modelParameter><spirit:name>PROG_ROM_WORDS</spirit:name><spirit:value>ROM_WORDS</spirit:value></spirit:modelParameter>
 <spirit:modelParameter><spirit:name>PROG_ROM_ADD</spirit:name><spirit:value>ROM_ADD</spirit:value></spirit:modelParameter>
 <spirit:modelParameter><spirit:name>VEC_TABLE</spirit:name><spirit:value>8'hff</spirit:value></spirit:modelParameter>
 <spirit:modelParameter><spirit:name>UART_PRESCALE</spirit:name><spirit:value>5'b01100</spirit:value></spirit:modelParameter>
 <spirit:modelParameter><spirit:name>UART_PRE_SIZE</spirit:name><spirit:value>5</spirit:value></spirit:modelParameter>
 <spirit:modelParameter><spirit:name>UART_DIV</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter>
 <spirit:modelParameter><spirit:name>JTAG_SEL</spirit:name><spirit:value>1</spirit:value></spirit:modelParameter>
 <spirit:modelParameter><spirit:name>JTAG_USER1_WIDTH</spirit:name><spirit:value>8</spirit:value></spirit:modelParameter>
 <spirit:modelParameter><spirit:name>JTAG_USER1_RESET</spirit:name><spirit:value>8'h12</spirit:value></spirit:modelParameter>

</spirit:modelParameters>





   





</spirit:model>    








</spirit:component>