Subversion Repositories socgen

[*]
[*] GTKWave Analyzer v3.3.62 (w)1999-2014 BSI
[*] Wed Apr 15 00:53:27 2015
[*]
[dumpfile] "/home/johne/Desktop/socgen/work/opencores.org__fpgas/ip/Nexys2_T6502/sim/icarus/jtag/TestBench.vcd"
[dumpfile_mtime] "Wed Apr 15 00:49:01 2015"
[dumpfile_size] 26939889
[savefile] "/home/johne/Desktop/socgen/Projects/opencores.org/fpgas/ip/Nexys2_T6502/sim/icarus/jtag/wave.sav"
[timestart] 103210000
[size] 1613 999
[pos] -1 -1
*-22.000000 112700500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] TB.
[treeopen] TB.test.
[treeopen] TB.test.dut.
[treeopen] TB.test.dut.core.
[treeopen] TB.test.dut.core.disp_io.
[treeopen] TB.test.dut.core.T6502.
[treeopen] TB.test.dut.core.T6502.adv_dbg.
[treeopen] TB.test.dut.core.T6502.adv_dbg.i_dbg_jfifo.
[treeopen] TB.test.dut.core.T6502.adv_dbg.i_dbg_jfifo.jsp_biu_i.
[sst_width] 476
[signals_width] 214
[sst_expanded] 1
[sst_vpaned_height] 559
@28
TB.test.RXD
TB.test.TXD
TB.test.VGABLUE[1:0]
TB.test.VGAGREEN[2:0]
TB.test.VGARED[2:0]
TB.test.VSYNC_N
TB.test.HSYNC_N
@22
TB.test.display_model.segment0[3:0]
TB.test.display_model.segment1[3:0]
TB.test.display_model.segment2[3:0]
TB.test.display_model.segment3[3:0]
TB.test.dut.core.disp_io.PosD[15:0]
@28
TB.test.TXD
TB.test.RXD
TB.test.dut.JTAG_TCK
TB.test.dut.JTAG_TDI
TB.test.dut.JTAG_TDO
TB.test.dut.JTAG_TMS
TB.test.dut.JTAG_TRESET_N
@22
TB.test.dut.SW[7:0]
TB.test.dut.core.disp_io.jtag_rpc.capture_value[7:0]
TB.test.dut.core.disp_io.jtag_rpc.update_value[7:0]
@28
TB.test.dut.core.disp_io.jtag_rpc.update_dr_clk
TB.test.dut.core.disp_io.jtag_rpc.capture_dr
TB.test.dut.core.T6502.adv_dbg.capture_dr_i
TB.test.dut.core.T6502.adv_dbg.biu_wr_strobe
TB.test.dut.core.T6502.adv_dbg.debug_select_i
@22
TB.test.dut.core.T6502.adv_dbg.input_shift_reg[52:0]
TB.test.dut.core.T6502.adv_dbg.jsp_data_out[7:0]
@28
TB.test.dut.core.T6502.adv_dbg.module_id_in[1:0]
TB.test.dut.core.T6502.adv_dbg.module_id_reg[1:0]
@22
TB.test.dut.core.T6502.adv_dbg.module_inhibit[3:0]
TB.test.dut.core.T6502.adv_dbg.module_selects[3:0]
@28
TB.test.dut.core.T6502.adv_dbg.rst_i
TB.test.dut.core.T6502.adv_dbg.select_cmd
TB.test.dut.core.T6502.adv_dbg.select_inhibit
TB.test.dut.core.T6502.adv_dbg.shift_dr_i
TB.test.dut.core.T6502.adv_dbg.tck_i
TB.test.dut.core.T6502.adv_dbg.tdi_i
TB.test.dut.core.T6502.adv_dbg.tdo_cpu0
TB.test.dut.core.T6502.adv_dbg.tdo_cpu1
TB.test.dut.core.T6502.adv_dbg.tdo_jsp
TB.test.dut.core.T6502.adv_dbg.tdo_o
TB.test.dut.core.T6502.adv_dbg.tdo_wb
TB.test.dut.core.T6502.adv_dbg.update_dr_i
TB.test.dut.core.T6502.adv_dbg.wb_clk_i
@22
TB.test.dut.core.T6502.adv_dbg.wb_jsp_dat_i[7:0]
@28
TB.test.dut.core.T6502.adv_dbg.wb_jsp_stb_i
TB.test.dut.core.T6502.adv_dbg.i_dbg_jfifo.jsp_biu_i.rd_fifo.CLK
@22
TB.test.dut.core.T6502.adv_dbg.i_dbg_jfifo.jsp_biu_i.bytes_free_o[3:0]
TB.test.dut.core.T6502.adv_dbg.i_dbg_jfifo.jsp_biu_i.data_o[7:0]
@28
TB.test.dut.core.T6502.adv_dbg.i_dbg_jfifo.jsp_biu_i.next_rd_fsm_state[1:0]
TB.test.dut.core.T6502.adv_dbg.i_dbg_jfifo.jsp_biu_i.pop
TB.test.dut.core.T6502.adv_dbg.i_dbg_jfifo.jsp_biu_i.r_fifo_en
TB.test.dut.core.T6502.adv_dbg.i_dbg_jfifo.jsp_biu_i.r_wb_ack
TB.test.dut.core.T6502.adv_dbg.i_dbg_jfifo.jsp_biu_i.rcz
@22
TB.test.dut.core.T6502.adv_dbg.i_dbg_jfifo.jsp_biu_i.rd_bytes_avail[3:0]
@28
TB.test.dut.core.T6502.adv_dbg.i_dbg_jfifo.jsp_biu_i.rd_bytes_avail_not_zero
@22
TB.test.dut.core.T6502.adv_dbg.i_dbg_jfifo.jsp_biu_i.rd_fifo_data_out[7:0]
@29
TB.test.dut.core.T6502.adv_dbg.i_dbg_jfifo.jsp_biu_i.rd_fsm_state[1:0]
[pattern_trace] 1
[pattern_trace] 0