Subversion Repositories socgen

<?xml version="1.0" encoding="utf-8"?>
<!--
//                                                                        //
// Author : John Eaton  Ouabache Designworks                              //
//                                                                        //
//   Copyright (C) 2010 Authors and OPENCORES.ORG                         //
//                                                                        //
//   This source file may be used and distributed without                 //
//   restriction provided that this copyright statement is not            //
//   removed from the file and that any derivative work contains          //
//   the original copyright notice and the associated disclaimer.         //
//                                                                        //
//   This source file is free software; you can redistribute it           //
//   and/or modify it under the terms of the GNU Lesser General           //
//   Public License as published by the Free Software Foundation;         //
//   either version 2.1 of the License, or (at your option) any           //
//   later version.                                                       //
//                                                                        //
//   This source is distributed in the hope that it will be               //
//   useful, but WITHOUT ANY WARRANTY; without even the implied           //
//   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR              //
//   PURPOSE. See the GNU Lesser General Public License for more          //
//   details.                                                             //
//                                                                        //
//   You should have received a copy of the GNU Lesser General            //
//   Public License along with this source; if not, download it           //
//   from http://www.opencores.org/lgpl.shtml                             //
//                                                                        //
-->
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
<ipxact:vendor>opencores.org</ipxact:vendor>
<ipxact:library>fpgas</ipxact:library>
<ipxact:name>Nexys2_T6502</ipxact:name>
<ipxact:version>chip</ipxact:version>  



  <ipxact:fileSets>

    <ipxact:fileSet>
      <ipxact:name>fs-syn</ipxact:name>

      <ipxact:file>
        <ipxact:logicalName></ipxact:logicalName>
        <ipxact:name>../verilog/copyright.v</ipxact:name>
        <ipxact:fileType>verilogSource</ipxact:fileType>
        <ipxact:userFileType>include</ipxact:userFileType>
      </ipxact:file>

      <ipxact:file>
        <ipxact:logicalName></ipxact:logicalName>
        <ipxact:name>../verilog/sram.load</ipxact:name>
        <ipxact:fileType>verilogSource</ipxact:fileType>
        <ipxact:userFileType>fragment</ipxact:userFileType>
      </ipxact:file>

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    <ipxact:name>syn</ipxact:name><ipxact:envIdentifier>:*Synthesis:*</ipxact:envIdentifier>
    <ipxact:language>Verilog</ipxact:language>
    <ipxact:modelName></ipxact:modelName>
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