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v 20100214 1
B 300 0  3600 1900 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 2050   5 10 1 1 0 0 1 1
device=io_vga_def
T 400 2250 5 10 1 1 0 0 1 1
refdes=U?
T 400 2400    0 10 0 1 0 0 1 1
vendor=opencores.org
T 400 2400    0 10 0 1 0 0 1 1
library=io
T 400 2400    0 10 0 1 0 0 1 1
component=io_vga
T 400 2400    0 10 0 1 0 0 1 1
version=def
P 300 200 0 200 10 1 1 
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=wdata[7:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 10 1 1 
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=addr[3:0]
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 4 0 1  
{
T 400 600 5 10 1 1 0 1 1 1 
pinnumber=wr
T 400 600 5 10 0 1 0 1 1 1 
pinseq=3
}
P 300 800 0 800 4 0 1  
{
T 400 800 5 10 1 1 0 1 1 1 
pinnumber=reset
T 400 800 5 10 0 1 0 1 1 1 
pinseq=4
}
P 300 1000 0 1000 4 0 1  
{
T 400 1000 5 10 1 1 0 1 1 1 
pinnumber=rd
T 400 1000 5 10 0 1 0 1 1 1 
pinseq=5
}
P 300 1200 0 1200 4 0 1  
{
T 400 1200 5 10 1 1 0 1 1 1 
pinnumber=enable
T 400 1200 5 10 0 1 0 1 1 1 
pinseq=6
}
P 300 1400 0 1400 4 0 1  
{
T 400 1400 5 10 1 1 0 1 1 1 
pinnumber=cs
T 400 1400 5 10 0 1 0 1 1 1 
pinseq=7
}
P 300 1600 0 1600 4 0 1  
{
T 400 1600 5 10 1 1 0 1 1 1 
pinnumber=clk
T 400 1600 5 10 0 1 0 1 1 1 
pinseq=8
}
P 3900 200 4200 200 10 1 1
{
T 3800 200 5  10 1 1 0 7 1 1 
pinnumber=vga_red_pad_out[2:0]
T 3800 200 5  10 0 1 0 7 1 1 
pinseq=9
}
P 3900 400 4200 400 10 1 1
{
T 3800 400 5  10 1 1 0 7 1 1 
pinnumber=vga_green_pad_out[2:0]
T 3800 400 5  10 0 1 0 7 1 1 
pinseq=10
}
P 3900 600 4200 600 10 1 1
{
T 3800 600 5  10 1 1 0 7 1 1 
pinnumber=vga_blue_pad_out[1:0]
T 3800 600 5  10 0 1 0 7 1 1 
pinseq=11
}
P 3900 800 4200 800 10 1 1
{
T 3800 800 5  10 1 1 0 7 1 1 
pinnumber=rdata[7:0]
T 3800 800 5  10 0 1 0 7 1 1 
pinseq=12
}
P 3900 1000 4200 1000 4 0 1
{
T 3800 1000 5  10 1 1 0 7 1 1
pinnumber=vga_vsync_n_pad_out
T 3900 1000 5  10 0 1 0 7 1 1
pinseq=13
}
P 3900 1200 4200 1200 4 0 1
{
T 3800 1200 5  10 1 1 0 7 1 1
pinnumber=vga_hsync_n_pad_out
T 3900 1200 5  10 0 1 0 7 1 1
pinseq=14
}