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reg [3:0]         enableY;   
reg               wait_n;   



assign mem_rdata = ext_rdata;



always@(posedge clk)
  if(reset)
                      begin
                      ext_add   <=  'b0;
                      ext_wdata <= 16'b0000000000000;
                      ext_rd    <= 1'b0;
                      ext_wr    <= 1'b0;
                      ext_cs    <= 2'b00;
                      ext_stb   <= 1'b0;
                      ext_ub    <= 1'b0;
                      ext_lb    <= 1'b0;
                      end
  else
                      begin
                      ext_add   <= {10'b0000000000, mem_addr[13:1]};
                      ext_wdata <= mem_wdata;
                      ext_rd    <= mem_cs && mem_rd;
                      ext_wr    <= mem_cs && mem_wr;
                      ext_cs    <= {1'b0,mem_cs};
                      ext_stb   <= mem_cs;
                      ext_ub    <= mem_cs &&  mem_addr[0];
                      ext_lb    <= mem_cs && !mem_addr[0];
                      end



always@(posedge clk)
if(reset || enable) 
   begin
   wait_n  <= 1'b0;
   enableY  <= 4'b0000;
   end   
else
if (mem_cs  && (mem_rd || mem_wr))  
   begin
     if(enableY == 4'b0100) wait_n  <= 1'b1;
     else                   enableY  <= enableY +4'b0001;     
   end
else
   wait_n <= 1'b1;  


assign mem_wait = ~ wait_n;


`VARIANT`MB
#(.BANK_RST(8'h00),
  .WAIT_ST_RST(8'h04))

ext_mem_interface_micro_reg
( 
             .clk            ( clk     ),
             .reset          ( reset   ),
             .enable         ( enable  ),
             .cs             ( cs      ),              
             .wr             ( wr      ), 
             .rd             ( rd      ),
             .byte_lanes     ( 1'b1    ),
             .addr           ( addr    ),
             .wdata          ( wdata   ),
             .rdata          ( rdata   ),
             .bank_cs        (         ),
             .bank_dec       (         ),
             .bank_wr_0      (         ),
             .wait_st_cs     (         ),
             .wait_st_dec    (         ),
             .wait_st_wr_0   (         ),

             .next_wait_st   ( wait_st ),
             .next_bank      ( bank    ),

             .wait_st_rdata  ( wait_st ),
             .bank_rdata     ( bank    ),


             .wait_st        ( wait_st ),
             .bank           ( bank    )

);