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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [rtl/] [verilog/] [top.gpio.rtl] - Rev 134

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reg       wait_n_reg;

always@(posedge clk)
if(reset || enable) 
   begin
   wait_n_reg  <= 1'b0;
   end   
else
    wait_n_reg <= 1'b1;  



assign    wait_n = wait_n_reg;

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