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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [sim/] [testbenches/] [verilog/] [top.ext.gpio] - Rev 131

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assign    enable            = 1'b1;
assign    reg_mb_cs         = 1'b1;
assign    cts_pad_in        = 1'b0;
assign    uart_rxd_pad_in        = uart_txd_pad_out;

assign    gpio_0_in        = 8'b0;
assign    gpio_1_in        = 8'b0;

assign STOP = 1'b0;
assign BAD = 1'b0;

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