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<?xml version="1.0" encoding="UTF-8"?>
<!--
//                                                                        //
// Author : John Eaton  Ouabache Designworks                              //
//                                                                        //
//   Copyright (C) 2010 Authors and OPENCORES.ORG                         //
//                                                                        //
//   This source file may be used and distributed without                 //
//   restriction provided that this copyright statement is not            //
//   removed from the file and that any derivative work contains          //
//   the original copyright notice and the associated disclaimer.         //
//                                                                        //
//   This source file is free software; you can redistribute it           //
//   and/or modify it under the terms of the GNU Lesser General           //
//   Public License as published by the Free Software Foundation;         //
//   either version 2.1 of the License, or (at your option) any           //
//   later version.                                                       //
//                                                                        //
//   This source is distributed in the hope that it will be               //
//   useful, but WITHOUT ANY WARRANTY; without even the implied           //
//   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR              //
//   PURPOSE. See the GNU Lesser General Public License for more          //
//   details.                                                             //
//                                                                        //
//   You should have received a copy of the GNU Lesser General            //
//   Public License along with this source; if not, download it           //
//   from http://www.opencores.org/lgpl.shtml                             //
//                                                                        //
-->
<ipxact:design 
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">

<ipxact:vendor>opencores.org</ipxact:vendor>
<ipxact:library>io</ipxact:library>
<ipxact:name>io_module</ipxact:name>
<ipxact:version>bfm.design</ipxact:version>  


<ipxact:vendorExtensions><socgen:nodes>

<socgen:node><ipxact:name>reg_mb_addr</ipxact:name>
<ipxact:typeName>wire</ipxact:typeName>
<ipxact:wire><ipxact:vector><ipxact:left>15</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:wire>
</socgen:node>



<socgen:node><ipxact:name>reg_mb_rdata</ipxact:name>
<ipxact:typeName>wire</ipxact:typeName>
<ipxact:wire><ipxact:vector><ipxact:left>15</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:wire>
</socgen:node>


<socgen:node><ipxact:name>reg_mb_wdata</ipxact:name>
<ipxact:typeName>wire</ipxact:typeName>
<ipxact:wire><ipxact:vector><ipxact:left>7</ipxact:left><ipxact:right>0</ipxact:right></ipxact:vector></ipxact:wire>
</socgen:node>


</socgen:nodes></ipxact:vendorExtensions>


  



 <ipxact:adHocConnections>

    <ipxact:adHocConnection>
      <ipxact:name>clk</ipxact:name>
      <ipxact:externalPortReference portRef="clk"/>
      <ipxact:internalPortReference componentRef="bus" portRef="clk"/>
    </ipxact:adHocConnection>

    <ipxact:adHocConnection>
      <ipxact:name>reset</ipxact:name>
      <ipxact:externalPortReference portRef="reset"/>
      <ipxact:internalPortReference componentRef="bus" portRef="reset"/>
   </ipxact:adHocConnection>


    <ipxact:adHocConnection>
      <ipxact:name>reg_mb_cs</ipxact:name>
      <ipxact:externalPortReference portRef="reg_mb_cs"/>
      <ipxact:internalPortReference componentRef="bus" portRef="cs"/>
    </ipxact:adHocConnection>


    <ipxact:adHocConnection>
      <ipxact:name>reg_mb_rd</ipxact:name>
      <ipxact:externalPortReference portRef="reg_mb_rd"/>
      <ipxact:internalPortReference componentRef="bus" portRef="rd"/>
    </ipxact:adHocConnection>


    <ipxact:adHocConnection>
      <ipxact:name>reg_mb_wr</ipxact:name>
      <ipxact:externalPortReference portRef="reg_mb_wr"/>
      <ipxact:internalPortReference componentRef="bus" portRef="wr"/>
    </ipxact:adHocConnection>





    <ipxact:adHocConnection>
      <ipxact:name>reg_mb_rdata</ipxact:name>
      <ipxact:externalPortReference portRef="reg_mb_rdata" left="7"  right="0"  />
      <ipxact:internalPortReference componentRef="bus" portRef="rdata"   />
    </ipxact:adHocConnection>


    <ipxact:adHocConnection>
      <ipxact:name>reg_mb_wdata</ipxact:name>
      <ipxact:externalPortReference portRef="reg_mb_wdata" left="7"  right="0"  />
      <ipxact:internalPortReference componentRef="bus" portRef="wdata"   />
    </ipxact:adHocConnection>


    <ipxact:adHocConnection>
      <ipxact:name>reg_mb_addr</ipxact:name>
      <ipxact:externalPortReference portRef="reg_mb_addr" left="ADDR_WIDTH-1"  right="0"  />
      <ipxact:internalPortReference componentRef="bus" portRef="addr"   />
    </ipxact:adHocConnection>


 </ipxact:adHocConnections>



<ipxact:componentInstances>




<ipxact:componentInstance>
<ipxact:instanceName>bus</ipxact:instanceName>
<ipxact:componentRef vendor="opencores.org" library="Testbench" name="micro_bus_model" version="def"   />
<ipxact:configurableElementValues>
<ipxact:configurableElementValue referenceId="addr_width">ADDR_WIDTH</ipxact:configurableElementValue>
</ipxact:configurableElementValues>
</ipxact:componentInstance>






</ipxact:componentInstances>
                









</ipxact:design>