URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_pic/] [rtl/] [verilog/] [top.body] - Rev 133
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reg [7:0] irq_act;
reg [7:0] nmi_act;
wire [7:0] irq_enable;
wire [7:0] nmi_enable;
parameter INT_IN = 4'h0;
parameter IRQ_ENABLE = 4'h2;
parameter NMI_ENABLE = 4'h4;
parameter IRQ_ACT = 4'h6;
parameter NMI_ACT = 4'h8;
always@(posedge clk)
if (reset)
begin
irq_act <= 8'h00;
nmi_act <= 8'h00;
irq_out <= 1'b0;
nmi_out <= 1'b0;
end
else
begin
irq_act <= irq_enable & int_in;
nmi_act <= nmi_enable & int_in;
irq_out <= | irq_act;
nmi_out <= | nmi_act;
end
`VARIANT`MB
#(
.IRQ_ENABLE_RST (IRQ_MODE),
.NMI_ENABLE_RST (NMI_MODE)
)
pic_micro_reg
(
.clk ( clk ),
.reset ( reset ),
.enable ( enable ),
.cs ( cs ),
.wr ( wr ),
.rd ( rd ),
.byte_lanes ( 1'b1 ),
.addr ( addr ),
.wdata ( wdata ),
.rdata ( rdata ),
.int_in_cs ( ),
.int_in_dec ( ),
.irq_enable_cs ( ),
.irq_enable_dec ( ),
.irq_enable_wr_0 ( ),
.nmi_enable_cs ( ),
.nmi_enable_dec ( ),
.nmi_enable_wr_0 ( ),
.irq_act_cs ( ),
.irq_act_dec ( ),
.nmi_act_cs ( ),
.nmi_act_dec ( ),
.irq_enable ( irq_enable ),
.nmi_enable ( nmi_enable ),
.irq_enable_rdata ( irq_enable ),
.nmi_enable_rdata ( nmi_enable ),
.int_in_rdata ( int_in ),
.next_irq_enable ( irq_enable ),
.next_nmi_enable ( nmi_enable ),
.irq_act_rdata ( irq_act ),
.nmi_act_rdata ( nmi_act )
);
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