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https://opencores.org/ocsvn/socgen/socgen/trunk
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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_ps2/] [sim/] [testbenches/] [verilog/] [tb.ver] - Rev 131
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assign enable = 1'b1;assign cs = 1'b0;assign ps2_clk_pad_in = 1'b1;assign ps2_data_pad_in = 1'b1;assign rd = 1'b0;assign wr = 1'b1;assign addr = 'b0;assign wdata = 'b0;assign STOP = 1'b0;assign BAD = 1'b0;