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wire xmit_data_wr;
wire  rcv_data_rd;



 `VARIANT`MB
  io_uart_micro_reg
( 
   .clk                ( clk                ),
   .reset              ( reset              ),
   .enable             ( enable             ),
   .cs                 ( cs                 ),        
   .wr                 ( wr                 ),
   .rd                 ( rd                 ),
   .byte_lanes         ( 1'b1               ),
   .addr               ( addr               ),
   .wdata              ( wdata              ),
   .rdata              ( rdata              ),


   .xmit_data_cs       (),
   .xmit_data_dec      (),
   .xmit_data          (),
   .next_xmit_data     (),
   .rcv_data_cs        (),
   .cntrl_cs           (),
   .cntrl_dec          (), 
   .cntrl_wr_0         (),
   .status_cs          (),
   .status_dec         (),
   .rcv_data_rdata     ( rcv_data           ),
   .status_rdata       ( status             ),
   .cntrl              ( cntrl              ),
   .cntrl_rdata        ( cntrl              ),
   .next_cntrl         ( cntrl              ),
   .xmit_data_wr_0     ( xmit_data_wr       ),
   .rcv_data_dec       ( rcv_data_rd        ));

   always@(posedge clk)
   if (reset)               txd_load <= 1'b0;
   else                     txd_load <= xmit_data_wr;



   always@(posedge clk)
   if (reset)               rx_irq <= 1'b0;
   else                     rx_irq <= cntrl[6] && rxd_data_avail;

   always@(posedge clk)
   if (reset)               tx_irq <= 1'b0;
   else                     tx_irq <= cntrl[7] && status[5];
  

 assign  status[0] = rxd_data_avail;
 assign  status[2] = 1'b0;
 assign  status[6] = 1'b0;
 assign  status[7] = 1'b0;


always@(posedge clk)
if (reset)     lat_wdata  <= 8'h00;   
else           lat_wdata  <= wdata;   


always@(posedge clk)
if (reset)     rxd_data_avail_stb  <= 1'b0;
else           rxd_data_avail_stb  <= (enable && rcv_data_rd  && rd);