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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_uart/] [sim/] [testbenches/] [xml/] [io_uart_tx_lint.xml] - Rev 131
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<?xml version="1.0" encoding="UTF-8"?><!--// //// Author : John Eaton Ouabache Designworks //// //// Copyright (C) 2010 Authors and OPENCORES.ORG //// //// This source file may be used and distributed without //// restriction provided that this copyright statement is not //// removed from the file and that any derivative work contains //// the original copyright notice and the associated disclaimer. //// //// This source file is free software; you can redistribute it //// and/or modify it under the terms of the GNU Lesser General //// Public License as published by the Free Software Foundation; //// either version 2.1 of the License, or (at your option) any //// later version. //// //// This source is distributed in the hope that it will be //// useful, but WITHOUT ANY WARRANTY; without even the implied //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// PURPOSE. See the GNU Lesser General Public License for more //// details. //// //// You should have received a copy of the GNU Lesser General //// Public License along with this source; if not, download it //// from http://www.opencores.org/lgpl.shtml //// //--><spirit:componentxmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"xmlns:socgen="http://opencores.org"xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"><spirit:vendor>opencores.org</spirit:vendor><spirit:library>io</spirit:library><spirit:name>io_uart</spirit:name><spirit:version>tx_lint</spirit:version><spirit:model><spirit:modelParameters><spirit:modelParameter><spirit:name>BUS_ADDR_WIDTH</spirit:name><spirit:value>4</spirit:value></spirit:modelParameter><spirit:modelParameter><spirit:name>PS2_MODEL_CLKCNT</spirit:name><spirit:value>8'h7f</spirit:value></spirit:modelParameter><spirit:modelParameter><spirit:name>UART_MODEL_CLKCNT</spirit:name><spirit:value>4'b1100</spirit:value></spirit:modelParameter><spirit:modelParameter><spirit:name>UART_MODEL_SIZE</spirit:name><spirit:value>4</spirit:value></spirit:modelParameter></spirit:modelParameters><spirit:views><spirit:view><spirit:name>Dut</spirit:name><spirit:vendorExtensions><spirit:componentRef spirit:vendor="opencores.org"spirit:library="io"spirit:name="io_uart"spirit:version="tx_dut.params"/></spirit:vendorExtensions></spirit:view><spirit:view><spirit:name>lint</spirit:name><spirit:envIdentifier>:*Lint:*</spirit:envIdentifier><spirit:language>Verilog</spirit:language><spirit:fileSetRef><spirit:localName>fs-lint</spirit:localName></spirit:fileSetRef></spirit:view><spirit:view><spirit:name>rtl_check</spirit:name><spirit:vendorExtensions><spirit:componentRef spirit:vendor="opencores.org"spirit:library="Testbench"spirit:name="toolflow"spirit:version="rtl_check"/></spirit:vendorExtensions></spirit:view></spirit:views></spirit:model><spirit:fileSets><spirit:fileSet><spirit:name>fs-lint</spirit:name><spirit:file><spirit:logicalName></spirit:logicalName><spirit:name>../verilog/lint/io_uart_tx_lint</spirit:name><spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType></spirit:file></spirit:fileSet></spirit:fileSets></spirit:component>
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