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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_utimer/] [rtl/] [verilog/] [top.body] - Rev 135

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parameter TIMER_LATCH  = 4'h0;
parameter TIMER_COUNT  = 4'h2;

   
wire [7:0]              count;
reg  [7:0]              next_count;
wire [7:0]              latch;

reg [5:0]              u_sec;


   


   

always@( posedge clk)
if(reset)                                                                     u_sec <= FREQ-1;
else
if((u_sec == 0) ||   (wr && enable  && cs && addr[3:0] == TIMER_COUNT) )      u_sec <= FREQ-1;
else                                                                          u_sec <= u_sec-1;



always@(*)
if(u_sec == 0)
  begin
  if(count == 8'h00)                                  next_count  = 8'h00;
  else
  if(count == 8'h01)                                  next_count  = latch;
  else                                                next_count  = count-1;
  end
else                                                  next_count  = count;



`VARIANT`MB
utimer_micro_reg
(
      .clk             ( clk        ),
      .reset           ( reset      ),
      .enable          ( enable     ),

      .cs              ( cs         ),
      .wr              ( wr         ),                 
      .rd              ( rd         ),
      .addr            ( addr       ),
      .byte_lanes      ( 1'b1       ),   
      .wdata           ( wdata      ),
      .rdata           ( rdata      ),

      .latch_cs        (            ),
      .latch_dec       (            ),
      .latch_wr_0      (            ),
      .count_cs        (            ),  
      .count_dec       (            ),
      .count_wr_0      (            ),


      .count           ( count      ),
      .latch           ( latch      ),

      .count_rdata     ( count      ),
      .latch_rdata     ( latch      ),

      .next_count      ( next_count ),
      .next_latch      ( latch      )   

);







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